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<OmniMancer> daveshah: is there any way to represent two generic slices in the generic backend having to share a clock?
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<daveshah> OmniMancer: the generic backend considers all slices in a tile to share a clock
<OmniMancer> ah okay :)
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<hackerfoo> AXI lite slave is a map from an address stream to a data stream on the read side, and a zip of address and data streams to a response stream on the write side, in functional terms. But the connection between the two sides is difficult to model functionally.
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<OmniMancer> daveshah: is it possible to express fixed connections in the generic nexpnr backend?
<daveshah> Just use a normal pip
<daveshah> In architectures with unidirectional routing this is fine (aiui anlogic will be like this)
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<daveshah> (there are some cases where this isn't enough, the solution is wire aliases but these aren't fully implemented yet)
<OmniMancer> I believe they are unidirectional
<OmniMancer> Is a tile the same set of x,why co-ords?
<OmniMancer> x,y
<daveshah> Yes
<OmniMancer> hmmm, some of the clock routing seems to involve setting 4 bits for some settings
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<daveshah> The central global clock routing on ECP5 is a fully decoded mux not a dual one-hot one
<OmniMancer> that may well be the case, what do the settings on such a MUX look like? every binary value of N bits?
<daveshah> Yeah, more or less
<daveshah> I think one of them is 6 bits but only 60 choices so 4 codes are missing
<OmniMancer> down to 371 unique bits that turn up as unknown in a ChipConfig now, but that is just using sort and uniq so the same relative bit in different tiles might go uncounted
<OmniMancer> Oh in the reference design I am using as a sort of representative normal soft cpu
<OmniMancer> Is that the routing to the clock spines?
<daveshah> Yeah, the selection between edge clock mux outputs and clock spine signals
<daveshah> The edge clock muxes themselves are also binary but with far fewer inputs (6-8 usually)
<OmniMancer> I mean at each tile, how many global clocks exist?
<OmniMancer> daveshah: does placement take routability into account?
<daveshah> No, that is usually something you implement in nextpnr via validity checks
<daveshah> The generic arch doesn't really provide these but is really designed for simple demos with one clock domain where this doesn't matter
<OmniMancer> indeed I am just wondering for later
<OmniMancer> its just there are an awful lot of feedback pips it seems
<daveshah> If you have a look inside arch_place.cc for iCE40 or ECP5 you can see an example of these checks
<OmniMancer> daveshah: how does one deal with special tile config bits that reside within the routing tile?
<daveshah> That's not really something I've seen
<OmniMancer> well I think they actually perform the same function as in the PLBs, its an invert bit for the SR signal
<daveshah> That probably just needs a sensible name and some code to deal with it during pnr bitgen
<daveshah> Although it only saves the odd LUT so it's probably not the most important feature
<OmniMancer> indeed, though the SR can be driven via the global clock tree
<OmniMancer> I think it won't need looking at unitl IO registers are needed
<OmniMancer> It's more the sort of philosophical database thing of where should that live
<OmniMancer> do the floor planner tools usually allow loading bit files?
<daveshah> No, I haven't seen this before
<OmniMancer> okay just making sure
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<azonenberg> daveshah: greenpak is the only tool i've found that can do that
<azonenberg> greenpak designer*
<OmniMancer> The IO routing seems a bit strange, since it seems like some of the pads from an IO block at one "location" are actually routed through pibs in a slightly different locaiton
<daveshah> That sounds quite possible
<daveshah> ECP5 BRAM and DSPs can have a bit of an offset
<OmniMancer> I suspect the BRAM and DSP tiles probably will have a similar thing since they likely use more than one tiles worth of IO
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<OmniMancer> daveshah: does it matter if you make wires that don't connect to anything?
<OmniMancer> or that have no drivers
<daveshah> No, that's absolutely fine
<OmniMancer> okay good, cause its easiest to just make all the local wires and then just not hook up the sources for interconnect that doesn't have source tiles
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<daveshah> OmniMancer: yeah, that's kind of how the ECP5 interconnect looks
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<tnt> "HeAP: support for bel region constraints"
<tnt> Oh, that's nice :)
<daveshah> Yeah, finally going to be the default for iCE40 too
<whitequark> excellent!!
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<ZirconiumX> ZipCPU: Did you ever do a DDR controller?
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<ZipCPU|Laptop> Zirconiumx: Nothing I've done has passed a hardware test
<ZirconiumX> That fills me with confidence...
<ZirconiumX> LiteDRAM seems difficult to use, especially because the examples are unhelpful and the source code undocumented.
<ZirconiumX> So I'm faced with the choice of trying to put up with it, or write my own DDR3 controller.
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