freemint has quit [Remote host closed the connection]
freemint has joined ##openfpga
freemint has quit [Remote host closed the connection]
freemint has joined ##openfpga
X-Scale` has joined ##openfpga
X-Scale has quit [Ping timeout: 246 seconds]
X-Scale` is now known as X-Scale
freemint has quit [Remote host closed the connection]
freemint has joined ##openfpga
genii has quit [Quit: Welcome home, Mitch]
rohitksingh has joined ##openfpga
davidthings has joined ##openfpga
nrossi has joined ##openfpga
davidthings has quit [Read error: Connection reset by peer]
davidthings has joined ##openfpga
davidthings has quit [Read error: Connection reset by peer]
davidthings has joined ##openfpga
azonenberg_work has quit [Ping timeout: 240 seconds]
Bike has quit [Quit: Lost terminal]
freemint has quit [Ping timeout: 250 seconds]
davidw has joined ##openfpga
davidthings has quit [Read error: Connection reset by peer]
davidw is now known as Guest73963
OmniMancer has joined ##openfpga
<OmniMancer>
keesj: It likely is the JTAG adapter being strange, its some kind of strange custom firmware on a gigadevice STM32alike that seems to just take JTAG signal vectors over USB to bitbang
iximeow_ is now known as iximeow
flaviusb has joined ##openfpga
<keesj>
or.. what I have seen more often is that the signaling level is not correct. more expensive jtag adapters will use vref for example of better handle higer reates or adaptive clocking.
<keesj>
I do like all the open source tools and still have a few JTAGGKey2 probes but I also evaluted dstream (and tools that come with it) and I have to confes the tool is superior and know much more about jtag (TAP controllers) en even more about ARM trace buffers and debug configuration.
<OmniMancer>
keesj: well the thing I am trying to communicate with is an FPGA so ARM debuggers are useless for that end
rohitksingh has quit [Remote host closed the connection]
rohitksingh has joined ##openfpga
<keesj>
true
<adamgreig>
is there any way in yosys/nextpnr to keep a module's ports without them actually getting connected to io pins? i.e. if i have some 32 bit interface to a module and i want to just get some rough resource and timing numbers in isolation, but don't have 32 IOs for nextpnr to automatically assign
<adamgreig>
i basically want to black box some modulewwwwwwwwww
<adamgreig>
-wwwww
<daveshah>
If its an ECP5 design, you can try --out-of-context (this isn't implemented for iCE40 yet)
<daveshah>
as a nextpnr option
<adamgreig>
ah cool, this is actually ice40 but that sounds like exactly the option i want :p
<adamgreig>
mostly just idle curiosity as right now i'm constantly sort of bodging modules into barebones designs with io etc just to get a handle on resource usage
freemint has joined ##openfpga
<pepijndevos>
mithro, do you have a copy of this table with all the pieces of the FPGA flow that I can use in a report?
freemint has quit [Ping timeout: 250 seconds]
<OmniMancer>
pepijndevos: congrats on getting a bitstream working
Guest73963 has quit [Remote host closed the connection]
<mithro>
pepijndevos: either of those?
Guest73963 has joined ##openfpga
<pepijndevos>
yea, the latter one, thanks :)
freemint has joined ##openfpga
<TD-Linux>
someone in china building one of my designs managed to get a fake ice40
<adamgreig>
does it work?
<TD-Linux>
apparently no. there could be other problems though
<daveshah>
Hah, never heard of fake iCE40s before
<Ultrasauce>
thats how you know lattice has finally Made It
Dolu has joined ##openfpga
<nats`>
Ultrasauce, siliconblue you mean :D
<Ultrasauce>
somehow doubt they were cloned before 2011 but sure
<whitequark>
you can remark anything you have in a suitable package, right
emeb has joined ##openfpga
<adamgreig>
can probably just buy blanks with custom markings these days too
<adamgreig>
or "blanks", whatever
<adamgreig>
can't use them for "process calibration" without a laser engraved xilinx logo :p
<TD-Linux>
these don't have a logo engraved
<daveshah>
The other nasty possibility with iCE40 is to simply recycle ones that have already had the NVCM programmed
<daveshah>
(these would even work fine if programming SRAM, but wouldn't boot from external flash)
freemint has quit [Quit: Leaving]
freemint has joined ##openfpga
dh73 has joined ##openfpga
Guest73963 has quit [Read error: Connection reset by peer]
freemint has quit [Quit: Leaving]
mkru has joined ##openfpga
mkru has quit [Client Quit]
mumptai has joined ##openfpga
Asu has joined ##openfpga
Asu has quit [Read error: Connection reset by peer]
Asu` has joined ##openfpga
Guest73963 has joined ##openfpga
azonenberg_work has joined ##openfpga
davidthings has joined ##openfpga
Guest73963 has quit [Read error: Connection reset by peer]
davidthings has quit [Read error: Connection reset by peer]
davidthings has joined ##openfpga
davidthings has quit [Read error: Connection reset by peer]
davidthings has joined ##openfpga
freemint has joined ##openfpga
freemint has quit [Ping timeout: 250 seconds]
freemint has joined ##openfpga
<adamgreig>
has anyone used the ice40up5k hard spi in anger? it seems like writing something to talk to the spi peripheral will take as many gates as just writing my own spi master
<Xark>
adamgreig: It is a bit of a pain (setting registers and using Wishbone bus). I have played around with a 6502 SoC design that uses hard SPI for Flash access that might be worth looking at for reference (done by emeb who is lurking). https://github.com/emeb/up5k_vga
<adamgreig>
thanks, i'll have a look
<adamgreig>
why bother with the hard spi, just because you were already using a similar bus?
<Xark>
adamgreig: I think in this case it was needed to access the flash that also holds the config for FPGA.
<Xark>
(So needed to be on hard SPI pins)
<adamgreig>
oh, I thought the flash pins were usable by normal user logic after configuration?
<Xark>
That may be also. I am not positive (emeb may have just wanted to excercise hard SPI with open toolchain).
<adamgreig>
yea, datasheet says the spi pins are usable as general i/o after configuration
<adamgreig>
fair enough
<adamgreig>
up5k_vga looks pretty cool, thanks for the link
nrossi has quit [Quit: Connection closed for inactivity]
finsternis has quit [Excess Flood]
rektide_ has quit [Ping timeout: 250 seconds]
finsternis has joined ##openfpga
rektide has joined ##openfpga
genii has joined ##openfpga
finsternis has quit [Ping timeout: 240 seconds]
finsternis has joined ##openfpga
rohitksingh has joined ##openfpga
cr1901_modern1 has joined ##openfpga
cr1901_modern has quit [Ping timeout: 240 seconds]
mumptai has quit [Quit: Verlassend]
rohitksingh has quit [Ping timeout: 250 seconds]
rohitksingh has joined ##openfpga
Asu has quit [Quit: Konversation terminated!]
cr1901_modern1 has quit [Quit: Leaving.]
cr1901_modern has joined ##openfpga
<tpw_rules>
tfw adding a barrel shifter reduces lut count and improves timing
Bike has joined ##openfpga
* emeb
unlurks...
<emeb>
Xark is right - I mainly wanted an excuse to try the SP_SPI core. Once I got it working though it's fairly easy to handle so I think it's a good choice to leave in.
<emeb>
OTOH, I do have some other iCE40 UP5k designs that needed SPI but had no internal CPU, so for those it was a *lot* easier to do a SPI interface in the fabric.
<adamgreig>
emeb: right, I don't have a cpu and just want to talk to an spi ADC, so probably fabric is the way to go
<emeb>
adamgreig: absolutely!
<adamgreig>
Very cool project though! I'm amazed how much fits in to the up5k
<emeb>
adamgreig: yeah - I've been able to shoehorn a lot of stuff into those. The DSP cores are pretty handy too - great for SDR stuff.
<adamgreig>
I have all 8 running decimation filters that churn through a staggering amount of data
<emeb>
Cool!
<adamgreig>
Hardest part is keeping them fed :p
<emeb>
heh
<adamgreig>
It's the one thing that makes the up5k really different to an hx8k I use elsewhere but has no hardware mac
<emeb>
I did a 50MSPS ADC -> 2-chl CIC decimator feeding a 512-tap FIR for my decimators. Nice sharp filter transitions w/o aliases.
<emeb>
main limitation is that the UP5k parts really don't like running much faster than 50MHz.
<whitequark>
tpw_rules: *how*
<adamgreig>
Yea I'm just targeting 50MHz flat on the up5k and generally hit it