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<tpw_rules>
can yosys infer SPRAMs on ice40?
<whitequark>
no
<tpw_rules>
also is the output registered? the usage guide implies it isn't
<whitequark>
it is
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<tpw_rules>
hm, the memory does not appear to be working. how might i debug this
<whitequark>
did you set the power saving mode correctly?
<tpw_rules>
i already fixed that (of course some are active high and some are active low). i just found out that i never actually assigned it to my submodules (wonder why forgetting an instance doesn't emit an UnusedElaboratable warning?)
<whitequark>
hm, because an Instance isn't an Elaboratable
<whitequark>
but that's a bad excuse
<tpw_rules>
but it still doesn't work
<tpw_rules>
fairly convinced my multiplexing logic is correct, since i can still address the other memory on that bus just fine, which is a BRAM
<tpw_rules>
i tried adding an output register but that didn't make it work
<tpw_rules>
whoops, never hooked up the address
<tpw_rules>
is there a way for a module to tell if it's running in simulation vs being elaborated? would be nice if i could e.g. automatically sub in an SPRAM emulator
<whitequark>
you can stuff the Instance full of any logic you want
<whitequark>
it's ignored during compilation to RTLIL or Verilog, and pysim, conversely, ignores the fact that it's an Instance
<tpw_rules>
but what if i want to replace the Instance with simulatable logic during simulation?
<whitequark>
that's what the above does
<whitequark>
normal memories actually work like that already
<tpw_rules>
i'm not sure i understand. how would i make my own Instance?
<tpw_rules>
with logc in it
<whitequark>
oh. hm. ok that's not really documented
<whitequark>
hmmm
<tpw_rules>
well, what is ;P
<whitequark>
so Simulator elaborates your stuff with `platform=None`
<whitequark>
you can branch on that
<tpw_rules>
ok
<tpw_rules>
good to know
<tpw_rules>
i was supposed to remind you to do something but i don't remember what :P
<whitequark>
right now i'm rewriting the simulator to not be so horribly slow
<tpw_rules>
ok that would be good too
<tpw_rules>
i'm about to start work on a uart bootloader, which should accelerate boneless screwing around ability dramatically
<whitequark>
okay
<tpw_rules>
then hopefully i can get SPI to work and bootload from flash too
<tpw_rules>
other random q, what endianness would you consider boneless? i know it doesn't matter for the actual thing but like should i stick to transmitting/storing images in a particular way?
<whitequark>
hm
<whitequark>
good question
<whitequark>
let's say big endian
<tpw_rules>
sounds good
<sorear>
if you wanted to compile C for it, you would need to decide on some representation for long and long long
<whitequark>
there's no toolchain that can compile C for it, i think
<whitequark>
sdcc and llvm don't do 16-bit bytes
<whitequark>
i'm not sure if gcc does, but i think it doesn't
<whitequark>
hm
<whitequark>
it does apparently
<whitequark>
tpw_rules: thinking more about it
<whitequark>
and considering what sorear says
<whitequark>
big integer arithmetics would be more natural in little endian, right?
<tpw_rules>
yeah
<tpw_rules>
that's the whole reason it exists, afaik
<whitequark>
ok so let's do little endian.
<tpw_rules>
equally sounds good
<whitequark>
everything else aside, 32-bit and wider arithmetic is pretty important
<tpw_rules>
well it messed up my documentation's word wrapping, so that's not good. but otherwise good
<whitequark>
word wrapping?
<tpw_rules>
i am an 80 column truther
<whitequark>
oh heh
<whitequark>
i use 120 these days
<tpw_rules>
the problem with that is that my laptop screen can only fit dual 83 column windows
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<zignig>
80 columns or death !! , phear the punch card!
* zignig
saw a mech puch card sorter, IRL
* zignig
old
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<mumptai_>
dont' be afraid of technical constraints of museum exhibits :)
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<pie_>
im guessing this lets you reconfigure all the doors in princeton
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<ZirconiumX>
I'm trying to build LiteX like in somlo's guide, but I get a compile error on libcompiler_rt's fixsfsi.c
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<pepijndevos>
What is this PRGA thing? You can just design your own FPGA?
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<Finde>
pepijndevos: yeah you design your FPGA
<Finde>
the goal is to give the flow for making the FPGA chip of your design, then also the flow for targeting your FPGA (yosys+vpr+...)
<somlo>
ZirconiumX: I won't be able to actually try anything until Monday, but in the mean time, is there a chance you're missing some sort of development package or library on your host system?
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<ZirconiumX>
somlo: I doubt it; compiler-rt isn't meant to depend on anything anyway
<somlo>
one more wild guess off the top of my head: something about the cross-compiler toolchain maybe ?
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<ZirconiumX>
somlo: That seems more likely, but it'll be a pain because I literally copy/pasted your instructions there
<somlo>
ZirconiumX: I have git commit afcc8bc (for riscv-gnu-toolchain); haven't updated that part in quite a while...
<somlo>
may be time to grab the latest available and make sure the LiteX bios compiles with it...
<somlo>
ZirconiumX: not sure it's worth your time to check out that older commit and rebuild the toolchain just to confirm that theory :)
<ZirconiumX>
Since it's 30 minutes to midnight, probably not, no :P
<somlo>
but it looks like they went from gcc 8 to 9 since last I looked, which presents ample opportunity for things to break :)