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<GenTooMan>
mithro that IC looks to be useful when coupled with an FPGA. Certainly more flexible than something from FTDI.
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<mithro>
GenTooMan: I was looking for the fx2 and randomly ended up at the sx2 page...
<GenTooMan>
mithro I was looking for ULPI PHY interfaces for USB2 ... this is much better it includes the PHY and an interface I don't have to use the FPGA to configure. Simplifying things. I looked at it but didn't read the data sheet.
<GenTooMan>
I suddenly feel like a cat with string dangling in front of it
<zignig>
or a laser pointer sticky taped to it's own head ?
<GenTooMan>
zignig that's quasi self inflicted madness. I've seen cats flush toilets for fun too... So hmm I guess I should look at options. Like anything start with a foundation so you have something to stand on.
<GenTooMan>
thanks for the heads up I appreciate having options when something else doesn't work.
<zignig>
no problem , carry on !! ;)
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<OmniMancer>
I suspect I might need to get a few complicated designs that use various slice features and use them to collect valid routing connections
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<zignig>
whitequark: calling conventions on the boneless? what was your intention with with windows ?
<zignig>
prelude copy , sliding awesome , or going to make it up as we went along ?
<adamgreig>
on ice40, if i want to sample an input on clock falling edge, is there any difference between using ddr with positive clock and only reading the second output, vs using sdr and feeding a negated clock? maybe the former doesn't require an inverter?
<whitequark>
the former is the only reliable way to do this, I think
<adamgreig>
doesn't seem like there's any disadvantage either so I guess I'll stick with that
<whitequark>
you probably want to re-register it (nmigen does this for you)
<adamgreig>
guessing an inverter only adds latency and placement-variable delay
<adamgreig>
for metastability issues?
<whitequark>
no
<whitequark>
because otherwise your Fmax will be halved
<whitequark>
it's only valid for half cycle after posedge
<whitequark>
nextpnr actually detects this correctly, itll just be slow
<adamgreig>
the SB_IO D_IN_1 is only valid for half a cycle? huh
<whitequark>
well, no, it's valid for one full cycle
<whitequark>
but it's phase shifted wrt your logic clock
<adamgreig>
oh right I see
<whitequark>
so there's only half cycle that's usable
<adamgreig>
only valid for half a cycle from the next rising edge
<whitequark>
yes
<adamgreig>
which is plenty of time to re-register it in logic
<adamgreig>
got it, thanks
<adamgreig>
this also seems like a nicer way to do spi than having a posedge and negedge clock domain and doing cdc and stuff
<whitequark>
yes
<whitequark>
there's a reason nmigen makes this the default
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<GenTooMan>
I suppose I need to upgrade yosys from 0.8 to 0.9 ... and hope that doesn't break things
<daveshah>
tbh, Yosys master is pretty stable
<daveshah>
Often less buggy than the last release
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<GenTooMan>
That is very good to know.
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<zkms>
i have an nmigen question; with FSMs, how can i set which state is the default/initial state?
<GenTooMan>
It looks like you pass that when you create the FSM class in python.
<GenTooMan>
IE <object> = FSM(<state>)
<GenTooMan>
The FSM class appears to be a class for compatibility with migen.