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<azonenberg> GenTooMan: ooh only 32 mbits? thats actually doable with a largeish fpga block ram
<azonenberg> you're well into kintex/virtex territory but it can be done on die
<azonenberg> alternatively, external QDR but you might have to gang a few to get the b/w
<GenTooMan> I suppose but eDRAM certain enhances the performance of the thing. as for memory I don't know of any DRAM devices that support QDR thus an expensive option possibly.
<GenTooMan> RDRAM is basically expensive and difficult to use, it also might require licensing from the idiots who license it just to use it. So likely that leaves just DDR3 devices.
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<azonenberg> GenTooMan: QDR is SRAM
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<ZirconiumX> sorear: I think it might be semi-feasible to double-pump an 8-pipeline GPU
<ZirconiumX> Although running it at 300MHz will be fun
<ZirconiumX> I'll have to scour ZipCPU's website pretty extensively for advice there :P
<tpw_rules> netburst™ gpu
<GenTooMan> azonenberg indeed the issues are QDR 1 expensive 2 power hungry 3 high end FPGAs only 4 they get hot regardless advantage you don't need to have a big FSM for read write and What The Heck as you need with DRAM
<ZirconiumX> tpw_rules: More pipeline stages! More of them!
<GenTooMan> pipeline dreams... :D
<ZirconiumX> Six stages so far, and I need to bolt on texturing units in front
<ZirconiumX> And the actual renderer at the end of it :P
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<GenTooMan> It will be interesting to see how you test this design. The big advantage might be that it isn't a PS2 so you can use HDMI for the output.
<ZirconiumX> GenTooMan: Indeed, though the conversion to something HDMI likes is going to be tricky
<ZipCPU> What would be the challenge with converting to HDMI? It's just a pixel stream ... (with minor formats)
<ZirconiumX> The PS2 can output in arbitrary resolutions, and I have to produce that arbitrary clock for the HDMI output
<ZipCPU> This worked on a Xilinx chip: https://zipcpu.com/blog/2019/06/28/genclk.html
<ZipCPU> Not sure if it'd still work on an ECP5 or even an iCE40 though, just never tried it
<ZirconiumX> Up to and including some of the games that switch resolutions on alternating frames
<ZirconiumX> This is not going to fit on an iCE40 :P
<ZirconiumX> An ECP5, maybe, but I don't think I could push an ECP5 hard enough for this
<whitequark> ZirconiumX: there's no OSERDES on ice40
<whitequark> er
<whitequark> ZipCPU:
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<whitequark> ZipCPU: but I have another question. why would you go through a pin and a PLL as opposed to simply using a BUFG on the output of an FF?
<ZipCPU> Two reasons: 1) I needed the OSERDES, and 2) it keeps Xilinx from complaining
<whitequark> oh wait, you're right, UG472 does not say that BUFG can have input from fabric
<whitequark> I am surprised, ice40 can buffer clocks from fabric just fine
<whitequark> wait, no
<whitequark> The possible sources for input to the global clock buffers include:
<whitequark> * Clock-capable inputs
<whitequark> * General interconnect
<whitequark> * ...
<whitequark> (page 36 of UG472)
<ZipCPU> I think it complains because the delay between the clock and anything else is uncontrolled when you go through the interconnect to get to it
<whitequark> that is true. but you could put your two clock domains in different groups, right?
<whitequark> then Vivado won't treat them as relate
<whitequark> *related
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