<freemint>
Artix7 200T is as fast in FPU as a GT730 (numbers from 2016). They are 3 times as expensive per clock but 10 more enery efficient at flops.
<kc8apf>
When to use an ASIC comes down to costs. A set of masks is $1+M. Engineering time can easily be more.
<freemint>
I thought you could save a lot by going to older nodes?
<kc8apf>
Per-die incremental costs are <$1
<kc8apf>
Sure. But then you're comparing what you can do with an FPGA on the latest node versus an ASIC on a much older node
<freemint>
ASICS for >11000$ you never stop learning
<sorear>
11k is damn cheap
<freemint>
what is the highest you have seen?
<freemint>
11k is probably more than all my networth as a student
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<sorear>
I've seen slides quoting >100M for tapeouts at leading nodes, but I think that rolls in a fair amount of design work, not just the fab itself
<kc8apf>
NRE on things like Google's TPUs is easily $100+M
<kc8apf>
Yup
<freemint>
Oh yes, sorry i misstyped, FPGAs for >11000$
<kc8apf>
Tools and design work is more than fab setup
<sorear>
xilinx and probably all other vendors fleece qty 1 buyers
<freemint>
I was supprised to see an FPGA which costs more than a decent car. Do you know how high the FPGA prices go?
<kc8apf>
Prices on top-end FPGAs are highly variable and never list price
<freemint>
ahh
<sorear>
if you wanted to build a f1.16xlarge from components at list price, you would spend about $200k
<kc8apf>
No one buys qty1 of those via a distributor
<sorear>
(nobody pays list price)
<sorear>
wait, I think it was 8x$45k
<freemint>
Are you aware of any cheap rented access to <= Spartan class FPGAs?
<freemint>
Those Amazon FPGA instances are a bit to high class for anything i have in mind. Having FPGA renting like there is for GPUs would be great.
<freemint>
Sorry i am tired as hell GN
<GenTooMan>
good night rest well
<GenTooMan>
I can understand NRE's and that's why those very expensive high end FPGA's are so important before you blow millions on a defective design. :D
<freemint>
I was just thinking about calling deutsche Telekom because they have 24/7 hotline for testing and they also offer FPGAs in their cloud ... when it is 3 am there ... .
<freemint>
what NRE?
<GenTooMan>
Non Reoccurring Engineering Fee for a design of an SoC IC those get expensive fast. You can chip the cost way down but eventually you have to pay I think I saw a few years back someone did a SoC multi-core Adaptiva was the companies name.
<sorear>
naive question, but what are you hoping to gain by having rented access to a spartan instead a virtex ultrascale
<sorear>
are you trying to use tools that only support spartan?
<sorear>
is your budget such that $1/hour for the f1.2xlarge is a lot of money?
<freemint>
Let's say some OSHW builds a new softcore and they want to unit test their design with each change they do.
<sorear>
unit tests are normally short and run in sim
<freemint>
No but f1.2x large is not FPGA which is targetted
<sorear>
why are you writing softcores that target specific fpgas
<freemint>
Maybe i said that badly. An f1.2x seems a bit overkill
<sorear>
in what way are you *hurt* by having extra capacity?
<sorear>
2ghz cpus are overkill for nearly everything, do you go out of your way to get 50mhz software testing machines?
<freemint>
Maybe this was just a stupid idea at night i have.
<freemint>
If someone has a semi-decent server somewhere and would give access to 4
<freemint>
Artix 7 to $person. would that be a good thing or would it be worthless to ##openfpga
<kc8apf>
I've asked about this in the past. Everyone wants some sort of CI system for FPGAs. I dunno what that ends up looking like.
<kc8apf>
Under what circumstances would a sim be insufficient but additional peripherals aren't required?
<kc8apf>
I've got a wide spectrum of FPGAs I could put online. I just have no idea in what configuration they would be useful
<freemint>
When you want to test that a Linux boots on your softcore and it can missuse the MMU as it want's without anything breaking? I think sim is >10.000x slower than FPGA
<kc8apf>
But that requires some specific, additional peripherals
<freemint>
How?
<kc8apf>
RAM
<freemint>
Right ... maybe having RAM next to the FPGA is worth having
<kc8apf>
But it wouldn't be on an iCE40
<freemint>
Depends on what board you put there for testing but right i see the problem
<freemint>
You could attach dev-boards but ... you find some flaw in that too i guess
<kc8apf>
Best I've come up with is having a 2nd FPGA emulating devices
<sorear>
f1 *does* give you ram
<kc8apf>
Similar to how Glasgow does applets
<kc8apf>
Is F1 useful as a CI system?
<freemint>
I have no idea but i guess it could be. Does anyone know how fat the FPGAs are in these machines?
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<kc8apf>
They are UltraScale+ with 64GB of RAM attached and x16 PCIe to host
<kc8apf>
xcvu9p-flgb2104-2-i
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