<adamgreig>
what tools do people use for sketching digital hardware designs beyond paper? inkscape's flowchart stuff is pretty irksome, graphviz could work but is a bit annoying for this, xfig?
<adamgreig>
maybe tikz...
<cr1901_modern>
openoffice draw
<cr1901_modern>
or libreoffice for ppl who actually keep their copy up to date
<adamgreig>
does it have anything to help with orthogonal nets and nicely aligned boxes and stuff? i've used it a bit in the past but not extensively
<cr1901_modern>
I don't remember offhand. Inkscape certainly does :P.
<adamgreig>
inkscape would be fine except for it comes with a load of things for flow charts and they're really annoying and I'd rather they just didn't exist :P
<azonenberg>
The last dedicated flowchart software i used was ABC FlowCharter for Windows 3.1
<azonenberg>
installing it off a dozen-odd floppies was a pain
<adamgreig>
what do you use for complicated digital logic these days, if anything? my notebook sketches are getting out of hand
<adamgreig>
hah
<azonenberg>
adamgreig: normally i do block diagrams in inkscape and then go straight to hdl
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<tnt>
adamgreig: I bought a digital epaper tablet just to draw logic diagrams by hand and have them as pdf afterward :)
<adamgreig>
ah, that sounds nice. can you also erase bits as you go?
<tnt>
Sure you can erase and even move blocks freely.
<emily>
tnt: cool, any recommendations? I hear about the reMarkable a fair bit
<tnt>
emily: That's the one I have.
<emily>
heh
<emily>
I would be more interested if I hadn't also heard it's not good as an ebook reader :/
<tnt>
I'm happy with it, it really feels like I'm drawing on paper. My main complaint would be I'd love a bit longer battery life. Also it's rather expensive :/
<tnt>
I used it a bit to read PDF documents, works OK, but "browsing" when you don't know exactly what you're looking for is a bit painful. I didn't really try to use it as a real ebook reader.
<tnt>
I know Sony epaper things are also supposes to be nice, but they are not availabe in EU so ...
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<adamgreig>
azonenberg: it turns out I needed more abstract block diagrams to understand what I was doing, not more detailed logic diagrams
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<hackerfoo>
I have a Boox Max 2 and it works well for diagrams and reading papers. It wasn't cheap, though. They have a Max 3 now.
<hackerfoo>
You can also use it as an HDMI monitor, but I haven't used that much.
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<daveshah>
tldr assert PROGRAMN to go to the next bitstream in the sequence
<daveshah>
there is no (known) way to trigger reconfiguration from fabric so you have to connect PROGRAMN to another FPGA pin to access it :/
<tnt>
it says "or issuing a REFRESH via any sysCONFIG port" ?
<daveshah>
Yes, that would be the other option
<tnt>
In either case, programn is fine. The board has that connected.
<daveshah>
sysCONFIG would be JTAG
<daveshah>
I'm not sure "any sysCONFIG port" is correct as iirc slave SPI conflicts with master SPI
<tnt>
But you can only go to the 'next' you can't select which one to boot ? It says there is up to 5 but I don't see how/where to specify addresses, or hardcoded values ?
<daveshah>
Addresses are specified in the bitstream (ecpmulti does this)
<daveshah>
There is no selection, it's just a sequence
<tnt>
Oh, so the current bitstream contains the address of where to go next, got it.
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<tnt>
Mmm ... ERROR: IO pin 'flash_sck$tr_io' constrained to pin 'U3', which does not exist for package 'CABGA381'.
<tnt>
I definitely do see a pin U3
<daveshah>
You need to use USRMCLK
<daveshah>
sck isn't a normal IO pin
<tnt>
Yup, just got that tx.
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<pepijndevos[m]>
How many seconds of 16 bit 48khz mono audio could you store in an ice40?
<daveshah>
Which iCE40? and compressed or uncompressed?
<pepijndevos[m]>
Up5k I guess, uncompressed
<pepijndevos[m]>
That's what the icebreaker has right?
<daveshah>
Yep
<pepijndevos[m]>
Just idle though from my phone about making a delay pedal
<daveshah>
The 128kB of SPRAM should do a bit over 1s
<pepijndevos[m]>
Is that kilo bits? Ah no spram is fixed 16 bit words, no?
<pepijndevos[m]>
Yea so 128/48=2.6 seconds?
<daveshah>
It's bytes
<tnt>
What would be the ECP5 equivalent of SB_GB ? I can't immediately find anything in cells_sim.v for ecp5
<daveshah>
DCCA
<daveshah>
you'll need fairly new nextpnr for manual instantiation (as opposed to promotion) to work correctly
<daveshah>
otherwise it would promote another one after it and waste a global
<tnt>
Is there some attribute I can put to force global instead of manual instanciation ?
<tnt>
Oh wait, it's for a widely used logic signal I need it, not for a clock.
<daveshah>
I think a DCCA should work for logic too
<daveshah>
It's not something I've actually tried
<tnt>
So nextpnr only promotes clocks atm ?
<daveshah>
Yes
<daveshah>
Diamond is pretty conservative about promoting stuff (sometimes resets and ces but rarely; never logic)
<tnt>
Ok, I'll leave it for now and see how it goes (it's for a reset signal ...)
<pepijndevos[m]>
Where do you find the amount of bram and spram? In this datasheets it appears as if it has 4 times 1024 kbit of spram and 30 times 120 kbit bram. So what's the 128kbyte figure coming from?
<daveshah>
4 is the number of blocks; 1024 kbit is the total size
<pepijndevos[m]>
(Not very effective browsing on my phone, maybe I'm just looking at the wrong thing )
<daveshah>
ditto for 30 and 120 k bit
<daveshah>
so it has 1024 kbits _total_ of spram (128kbyte)
<daveshah>
plus 16kbyte of bram but i wasn't counting that is it is only small in comparison and you might need it for other minor tasks
<tnt>
and 30 EBRs of 4kbits each.
<pepijndevos[m]>
Ah I see units are hard at this time apparently
<pepijndevos[m]>
Thanks
<tnt>
(seriously, how hard was it to cram 32 in there lattice ...)
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<pepijndevos[m]>
Okay so you're 101% correct about a bit over one second... 1.36533 seconds to be exact
<daveshah>
tnt: when noone who designed the fabric around and your whole chip is a hack :/
<daveshah>
(the up5k fabric is a ultra4k stretched by 1.5x in one direction - the CRAM banks which were always even before are uneven on the up5k as a result)
<daveshah>
*is around
<tnt>
heh, yeah, could have been better. But I still love it :p
<daveshah>
Yeah :)
<daveshah>
Will be interesting to see when they finally manage the ice40+ecp5 hybrid that has been rumoured for a while
<daveshah>
hopefully next year
<mwk>
the... what?
<daveshah>
well, it's a new arch designed to replace both families
<daveshah>
i suspect closer to ecp5 as that's the original lattice arch
<ZirconiumX>
But the real question is will they use a sane flip-flop naming scheme?
<daveshah>
Unlikely
<cr1901_modern1>
hopefully the tile names are regular like ECP5...
<daveshah>
Details are scarce unfortunately - all that's public is "investor level"
<daveshah>
still LUT4; more memory and DSP; 28nm FDSOI; "edge AI"
* ZirconiumX
laughs in arriav_lcell_comb, stratixv_ram_block and dffeas as primitive block names for the Cyclone V
* mwk
likes gowin "tile names"
<mwk>
they decided to use single-letter names
<mwk>
it started kind of ok
<mwk>
then they started running out of letters
<mwk>
and they started assigning random ones
<mwk>
then they run out of letters and started using symbols
<daveshah>
wow
<mwk>
so uh
<mwk>
a DSP is made of 9 tiles, of types: 012345678
<mwk>
a blockram is 3 tiles: cem
<mwk>
and a PLL (one kind of them at least) is: (_)%
<ZirconiumX>
Finally, an FPGA that reads like line noise
<cr1901_modern1>
galaxy brain: You can't run out of numbers...
<TD-Linux>
fortunately we've been adding emoji at rapid pace. they will be able to keep that convention for years to come
<daveshah>
just follows maths and physics and use greek letters
<mwk>
TD-Linux: the field is 8-bit unfortunately
<mwk>
I sure hope they don't intend to use iso-latin-1
<cr1901_modern1>
Use 0xFF as in band control info
<sorear>
pick a codepage
<sorear>
halfwidth katakana for style points
<mwk>
cr1901_modern1: hard to do when you store your fpga as an "unsigned char mah_fpga[200][150];" field in some C struct
<mwk>
er, or [150][200]
<mwk>
stupid multidimensional arrays
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<tnt>
Is there an example of ECP5 DDR IO registers ?