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<tnt> Is there some internal diagram of the ECP5 IO ? I find them rather obscure ... The ice40 io diagram might ot be perfect, but it's pretty easy to understand and get an idea of what does what. The fpga library description for the ecp5 are not always super clear :/
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<tnt> Yeah ... and I don't find it great either.
<tnt> Like for instance, ODDRX1F , D0/D1 description is "D0 is sent out first". But that doesn't tell me which edge they're output on. Like is it like in the ice40 with D0 being the falling edge output, or more like in Xilinx with the dual register for the falling edge and D0 will be the next rising edge and D1 the falling edge after that.
<daveshah> I need to write sim models, really
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