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<filt3r> ok, stupid question, but how do you (people in the "industry") see open fpga stuff in the future?
<filt3r> because i dont have much clue about the industry, but my thesis advisor basically laughed in my face when i mentined verilator ...
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<hackerfoo> filt3r: There is certainly interest, because the proprietary tools have restrictive licences that make using them difficult to use in many situations.
<hackerfoo> s/to use//
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<filt3r> ye, i mean from the discussion with my advisor i had the feeling like he never had to deal with licensing stuff ... or idk. i also have the feeling he is just used to the way it always has been (using vendor tools) and everything else is just toys for hobbyists and i have the feeling that this might be the attitude of many people in the industry
<filt3r> but ye i'm just letting of some steam here :)
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<filt3r> also including "classical" arguments like "the companies spent millions of man-hours for developement", "the internal fpga layout is a secret" or "you can't hold someone liable when using open source stuff" ... and yes, all of those points have some merit, it's just frustrating to me coming from the software side
<filt3r> ./rant over :)
<sorear> also “if the layout is secret, we won’t be sued for violating everyone else’s patents”, “we want to avoid having small customers because we lose money on support”, and “altera v. clear logic”
<sorear> all arguments I’ve heard
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<hackerfoo> On the other hand, I bet hardware companies would love if they could just ship cool hardware and let others worry about how to program it. That's not realistic, but open source software could allow them to focus more on hardware.
<Ultrasauce> licensing IP cores is a huge part of their business & a foss ecosystem will compete for a chunk of that market
<bubble_buster> hmm. I have libftdi-devel installed and have verified that lsusb changes when I use this usb cable on my phone, but when I plug in icebreaker, I see no change in lsusb output :(
<bubble_buster> is there some other driver required other than libftdi-devel?
<bubble_buster> I did restart just in case the driver needed to be loaded at boot or something, but it didn't help
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<ZirconiumX> filt3r: I think the biggest problem they'll have is that if someone compares the FOSS toolchain speed to the proprietary one, it becomes difficult to argue for the proprietary toolchain
<ZirconiumX> Yosys and nextpnr are *fast* by comparison, and that results in increased developer productivity.
<tnt> ZirconiumX: Huh, having worked for years as FPGA designer, at least where I worked, we spent 99% of our time in simulations ...
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<pepijndevos> tnt, so do you ever optimise for area/speed, or just throw money at bigger/faster FPGAs? Maybe also depends on if the domain requires lots of testing with actual hardware
<tnt> pepijndevos: We were definitely optimizing for area/speed quite a bit. Down to instanciating LUT manually for the critical path etc ...
<tnt> And in what I do today, I still do it. Mostly because I do a lot of "we have an existing deployed hardware, we now have to support XXX ... make it fit in there".
<ZirconiumX> tnt: sure, but doesn't that optimisation cycle result in a modify/compile loop where you're waiting on things to build?
<tnt> ZirconiumX: I can't really comment on that until we have a full PNR flow for a "large" chip. Build cycles I deal with are in the hours range. If open-flow cuts that in half, that's great ... if it cuts out 5% ... that doesn't matter.
<ZirconiumX> How large is large? :P
<tnt> Like kintex-7 325T, that kind of stuff.
<tnt> It's not even _that_ large in the grand scheme of thing, but still quite a bit more than a 85F.
<tnt> I guess comparing build results between diamond and a nextpnr on a ~ 80% full 85F design could already provide some interesting data point
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<pepijndevos> What's the largest open source tools currently support? From a quick google Kintex-7 has 478k cells
<pepijndevos> ZirconiumX, for the record, the cyclone V stuff we were doing freqently took like 10 minutes, will be interesting to see how fast mistral goes
<ZirconiumX> That's been my general experience with Quartus, yes
<ZirconiumX> Truthfully I'm a little uncertain I can RE the bitstream, because it's going to require a lot of my attention, which is a rather scarce resource >.>
<tnt> pepijndevos: The ECP-585F
<pepijndevos> So uh, like a fifth of a Kintex-7
<tnt> pepijndevos: this has 85k LUTs, but those are LUT-4, the 7-series is LUT-6 also the 7-series cells have multiple FFs.
<pepijndevos> Ehhh I see
<sorear> the xilinx parts are advertised using fake lut4 numbers that don’t map to the number of physical lut6
<emily> "the companies spent millions of man-hours for developement" - a case of the mythical man month if I've ever heard one >_>
<ZirconiumX> And then you have the Altera parts which are marketed with some weird, weird numbers
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<ZirconiumX> For example, they report thousands of LEs
<ZirconiumX> Where there are 2.5 LEs to an ALM
<ZirconiumX> Which makes...no sense
<daveshah> As far as I can tell the numbers are mostly an arms race with Xilinx
<ZirconiumX> And it's difficult to tell whether an ALM counts as "four LUT4s" or "a LUT 6"
<daveshah> Ultrascale uses 2.18 ish logic cells per LUT6
<emily> didn't xilinx just announce some even more ridiculously huge fpgas recently
<ZirconiumX> Even more confusingly, the ALM can sometimes go up to a LUT7
<ZirconiumX> Which is something I'm not even sure Yosys can express
<ZirconiumX> At least, not without a C++ pass to rewrite RTLIL
<daveshah> Probably using discrete LUTs and muxes would be a good start
<daveshah> This is how we represent these structures for other FPGAs
<daveshah> (eg synth_xilinx can map wide multiplexers to LUT and MUX combinations)
<ZirconiumX> That seems reasonable enough
<daveshah> It would only be a small custom pass then to combine them into a single LUT7 if needed
<ZirconiumX> Though given wq's comments, it seems like the modern way to go about this is to use ABC9?
<ZirconiumX> s/comments/comments in the past/
<daveshah> I still don't think that can map this kind of structure, but you would definitely want that for other reasons like mapping different sized LUTs correctly and handling hard blocks that have been instantiated (like MUX primitives from mux mapping)
<emily> something something flowmap?
<daveshah> Yeah, that could probably be hacked to deal with this structure too
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<azonenberg> So another thing that i would like to see in the open world is a good, fast simulator that supports systemverilog as well as design partitioning into multiple threads
<azonenberg> manual partitioning to start but ideally automated down the road
<azonenberg> If i have a big SoC that has dozens of blocks connected via axi or some kind of noc, i should be able to run each one separately and then just synchronize any time there's a bus transaction between them
<azonenberg> But highest priority for me remains support for sv structs and enums in yosys formal, with support for full synthesis being second
<azonenberg> i've basically been out of the formal game since i moved to SV
<daveshah> I don't think there is any difference between support for synthesis and formal?
<daveshah> The first stages of formal in Yosys are just word-level synthesis, by which point any data structures would be long gone anyway (they would be an elaborator thing moslty)
<azonenberg> sorry i meant, full synthesis for 7 series
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<tnt> Shot in the dark, but has anyone compared yosys / nextpnr under like a i9-9900K vs Ryzen-3700X ?
<azonenberg> tnt: i havent used nextpnr a ton but my experience with yosys itself on designs to date has been that synthesis is usually too fast to usefully benchmark :p
<tnt> yeah, I added yosys for completeness :p Mostly nextpnr is what takes time for me.
<tnt> Although ... when somehow a memory doesn't map to BRAM, yosys suddently takes forever :p
<ZirconiumX> Mostly because a BRAM that doesn't map has to be turned into possibly thousands of D flip-flops
<tnt> Yeah, I know and thousands is generous :)
<tnt> I wish there was a yosys option to abort in that kind of case, like a memory that that's more than XX FFs just aborts synthesis with error.
<azonenberg> As long as it's configurable
<azonenberg> i've worked on projects with several KB of DFF based memory on purpose
* zignig has has a relivation.
<zignig> can _we_ get all the nmigen_boards and put [minerva|boneless] on them for structural reconfiguation please...
<tnt> what's minerva ?
<whitequark> risc-v core in nmigen
<ZirconiumX> I am really struggling with understanding SRT division. Restoring/nonrestoring made sense, but SRT and anything more advanced does not
<ZirconiumX> Ugh
<ZirconiumX> I must be missing something >.>
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<zignig> whitequark: looking for a REPL to build a thing, Boneless needs 48MHz and a LLVM target.... pls.
<zignig> ZirconiumX: how goes your explorations ?
<ZirconiumX> So, to do shading, I need to be able to lerp across colour channels
<ZirconiumX> This requires a division to calculate the change in colour over the distance of the line
<whitequark> boneless needs LLVM?
<zignig> whitequark: it does not , but as a _not_ asm target the plebs can play.
<whitequark> "the plebs"?
<whitequark> spare me your arrogance.
<zignig> whitequark: no offence , it was a slight, just making trouble.
<zignig> ;))
<whitequark> that was not funny
<zignig> ok, when you are making glasgow widgets, where do you draw the line on gateware ?
<zignig> is it where it works ? , or do you have a line that you draw ?
<whitequark> I'm not sure what you're asking
<whitequark> what do you mean by "draw the line" exactly
<zignig> when you are build a new target for glasgow, how do you fine the _interior_ and the _exterior_ ?
<whitequark> I still don't understand the question
<zignig> hmm, rephrase.
<zignig> when you build an interface , part of is python feeder and some is gateware.
<tpw_rules> i think he's asking what part of the logic goes in the gateware and what part goes in the software?
<zignig> how do you fine the boundary ? by delving down or you just _know_
<zignig> *find
<whitequark> ah
<whitequark> in general, the timing critical parts stay in gateware
<whitequark> everything else in software
<zignig> nice to know.... :)
* zignig bows to one of the mistresses of gateware.
* zignig out.
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<ZirconiumX> wq: Are you watching Lucky Star now?
<whitequark> nope
<ZirconiumX> Huh, the "chocolate hornet" joke seemed like a blatant Lucky Start reference
<ZirconiumX> s/Start/Star
<whitequark> it is
<whitequark> i don't need to be watching it to reference it
<ZirconiumX> Ah, fair enough, sorry :P
<ZirconiumX> Neon Genesis Evangelion: Does What Nintendon't
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<cr1901_modern> Neon Genesisn't Evangelion
<ZirconiumX> Can somebody link me to a guide on implementing radix-4 SRT division? I've scoured the internet and found lots of papers, but no guides
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<pie_> any of you ever bought one of those cheap chinese ultrasonic cleaners or something? (id like one for my glasses)
<whitequark> i have
<emeb> putting eyeglasses into one of those can produce some horrifying results. seeing the quantity of dirt that billows out of the crevices from apparently clean glasses is startling.
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<whitequark> yeah kinda
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<pie_> so, the obvious question - anything i need to pay attention to? will this end horribly? etc?
<pie_> some googling suggests do not let the glasses touch anything other than the water but should otherwise be fine
<whitequark> basically yes
<pie_> there was some optics forum that was like "but muhhh delayering!!!"
<pie_> which is to say, something something bad for ...i forget the word, fancy optical layers? dunno about normal glasses
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<azonenberg_work> TIL
<azonenberg_work> the xc7v585T has two HR banks, and the xc7vc330t has one
<whitequark> HR?
<azonenberg_work> I thought all virtex7 were 100% HP
<azonenberg_work> whitequark: HR = high range, 3.3V/2.5V compatible but slower
<azonenberg_work> HP = high performance, maxes out at 1.8V but a lot faster
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<whitequark> ah
<whitequark> btw
<azonenberg_work> for example in a -2 speed kintex7 you can do LVDS up to 1.25 Gbps in a HR bank but 1.4 Gbps in a HP
<whitequark> what's the problem with making 3V3 IO faster
<azonenberg_work> in a -3, HR is no faster but HP gets to 1.6
<pie_> the word i was looking for was coating. so yeah do you guys have any recommendations for devices, or do i just grab some random thing off amazon?
<whitequark> do you just need larger transistors
<azonenberg_work> whitequark: fets that can handle higher voltage need thicker oxide and probably higher Vt
<whitequark> ah right
<azonenberg_work> This is the first time xilinx has had a full split though
<azonenberg_work> in 6 series and before, they had both types of drivers in one bank and just had a bitstream bit to specify the mode
<gruetzkopf> man these things have gotten FAST
<azonenberg_work> in 7 series there is still a bit (or several) for voltage range of the io bank
<whitequark> huh
<azonenberg_work> in HR banks at least
<azonenberg_work> but for whatever reason they couldn't manage to squeeze max speerd out
<azonenberg_work> conjecture: the switching circuitry to have two sets of drivers adds capacitance somewhere
<azonenberg_work> so the only way you can get max performance is by omitting the high voltage buffer
<gruetzkopf> what's behind these IOs to get data there that fast?
<gruetzkopf> that's gotta be more than just a DDR buffer
<azonenberg_work> gruetzkopf: the 7 series io cells have a SERDES in them, although without fancy clock recovery/PLL logic
<whitequark> xilinx has OSERDES for ages, no?
<azonenberg_work> yeah
<whitequark> since virtex-4 or earlier
<azonenberg_work> So you can have an 8-bit wide interface at 156.25 MHz and spit that out the IOs as LVDS at 1250 Mbps
<gruetzkopf> ah
<gruetzkopf> (last xilinx part i seriously used was XC3S-E stuff, so, OLD)
<azonenberg_work> i think that was the last genertion of xilinx stuff to not have ioserdes
<azonenberg_work> lol
<whitequark> yeah
<daveshah> I'm pretty sure Lattice experimented with 2Gbps on pins at one point
<daveshah> (not transceivers)
<daveshah> ECP4 was also planned to have those, shame it was penny pinched to 800Mbps for ECP5
<whitequark> penny pinched specifically?
<daveshah> Well, ECP4 was aimed at being top-of-the-line whereas ECP5 was mostly about competing on price
<daveshah> so perhaps not entirely fair
<daveshah> still, 2Gbps pins would be quite fun, if not that useful
<whitequark> right
<whitequark> wasn't there a problem where xilinx uhhhh
<whitequark> had completely uncalibrated IO delay on some spartans?
<gruetzkopf> 1250 on a LVDS pair is very useful though
<azonenberg_work> fpgas in their natural habitat :p
<whitequark> lol
<azonenberg_work> (this is what happens when you let marketing plan the photo shoots)
<daveshah> Perhaps a shipping container of them spilt
<azonenberg_work> this is the actual marketing image on avnet
<azonenberg_work> whitequark: re io delay, on spartan-6
<azonenberg_work> this wasnt a "problem" or "bug"
<azonenberg_work> there was, by design, no hard calibration circuit for the io delay so it was extremely ptv dependent
<whitequark> i mean
<whitequark> it's a problem if you want to use it.
<whitequark> it might not be considered a problem for xilinx.
<azonenberg_work> well, you were expected to implement closed loop feedback in fabric
<azonenberg_work> in order to compensate for the unknown phase delays
<azonenberg_work> basically constantly sweeping back and forth to stay centered in the eye
<whitequark> sounds like a problem, albeit solvable one
<whitequark> hm
<whitequark> i wonder if i could use ECP5's iodelay blocks to do a sort of DPLL for USB
<whitequark> i feel like i've been thinking about this before
<azonenberg_work> whitequark: what exactly are you trying to do?
<azonenberg_work> and what speed of usb?
<whitequark> HS of course, LS/FS can be done on iCE40 with no special tricks
<azonenberg_work> i was more wondering about HS vs SS
<whitequark> SS isn't interesting, you just set up the SERDES like you're supposed to
<whitequark> HS is... complicated
<whitequark> i'm not sure if the ECP5 SERDES can lock onto it
<azonenberg_work> I haven't looked at HS yet. Is it just LS/FS but faster?
<azonenberg_work> you almost certianly cannot get a pll to lock to that
<azonenberg_work> (i know its not a free running clock)
<whitequark> it's sort of like LS/FS
<azonenberg_work> What i have done in the past for weird fast-ish stuff is just oversample and do cdr in gateware
<whitequark> yes but it's a bit too fast for that
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<whitequark> you can oversample it with a normal IO pin on ECP5 by a factor of 2
<azonenberg_work> Xilinx has a fun capability, in 7 series at least, that lets you do ~5 Gsps on a differential input
<whitequark> which is not enough
<daveshah> Strictly speaking even that is out of spec
<whitequark> yeah, you can't do it on ECP5
<whitequark> yeah.
<azonenberg_work> basically, the differential input buffer has the option of outputting both legs of the diffpair
<azonenberg_work> you then run both through iodelays with different offsets
<azonenberg_work> and then separate iserdes's
<azonenberg_work> there's some fun trickery involved but you basically end up oversampling at 4x the data rate
<whitequark> actually
<whitequark> i don't think you can use ECP5 SERDES to implement USB HS
<whitequark> i don't think it has an OE
<azonenberg_work> this is how sgmii on lvds io's work
<azonenberg_work> on kintex7, which i'm doing on my switch
<whitequark> oh, there is
<azonenberg_work> you don't get a full recovered clock, but you can oversample to recover the data
<whitequark> "tx_idle_c"
<daveshah> but only registered, not ddr, outside of memory mode
<whitequark> daveshah: no i mean the 3G/5G SERDES
<daveshah> ah
<whitequark> it's undocumented other than one diagram
<whitequark> appears tohave been added solely for PCIe
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<ZirconiumX> I have created something of a monster and I'm reasonably sure it won't work. But it'll be fun to find out.
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