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<Sprite_tm> Hey, anyone has some experience with -abc9 on ECP5? It fails for me with an assert
<Sprite_tm> ERROR: Assert `!w->port_input' failed in passes/techmap/abc9.cc:97.
<Sprite_tm> This is with yosys/nextpnr/trellis updated just a few minutes ago.
<daveshah> I haven't seen that one before, but I've been away so haven't rebuilt in the last few days
<daveshah> Looking at where the assertion is, I expect it is a tristate related issue
<daveshah> I'd create a GitHub issue as Eddie will probably be able to fix that code better than I could
<Sprite_tm> Gotcha. Any ideas on how to trim this down a bit? I'm running this on a pretty large SoC, and the error gives no indication on where the problem is.
<mithro> kc8apf: What was that binary format description thingy
<mithro> kc8apf: Just watching the talk about poke at OrConf right now
<daveshah> mithro: kaitai?
<daveshah> Sprite_tm: you could try bugpoint
<mithro> daveshah: Yeap!
<daveshah> It tries to minimise a failing design
<Sprite_tm> Fancy, that should allow me to both work around the issue and file a nice bug report. I'll check it out.
<Sprite_tm> ...And I'm confused. bugpoint seems to run into the error and then just... gives up?
<Sprite_tm> -- Running command `bugpoint -script bugscript.txt' --
<Sprite_tm> ERROR: Assert `!w->port_input' failed in passes/techmap/abc9.cc:97.
<Sprite_tm> Demoting introduced module ports.
<Sprite_tm> Simplifications exhausted.
<ZirconiumX> Sprite_tm: you'll want to add something like "-grep passes/techmap/abc9.cc:97"
<Sprite_tm> Gotcha. It's a shame there isn't a simple example on how to use this...
<Sprite_tm> Also, what should I look for when it's done? Will it have deleted 99% of my .v files, or is the result somewhere else?
<daveshah> You probably want something like `proc; hierarchy` at least before bugpoint
<daveshah> It will leave the minimised design in Yosys
<daveshah> Then you can run write_ilang to save an il of it
* Sprite_tm is puzzled... so something like yosys -p 'proc; hierarchy; bugpoint -grep passes/techmap/abc9.cc:97 -script bugscript.txt; write_ilang' ?
<Sprite_tm> and script.txt contains the read -sv and synth_ecp5 lines?
<daveshah> No the read -sv needs to go before bugpoint
<daveshah> Otherwise, it has nothing to minimise
<ZirconiumX> Alternatively you can pass the file as an argument here and Yosys will read it, I think
<daveshah> In fact, try something like `read -sv ...; synth_ecp5 -run :map_luts; bugpoint ...`
<daveshah> Then `synth_ecp5 -run map_luts:` in the bugpoint script
<daveshah> That way it will really try and minimise the test case right before abc9
<daveshah> *add -abc9 to each synth_ecp5
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<Sprite_tm> This is what I have now, should this work? https://pastebin.com/xZ80jP2y
<Sprite_tm> Cause it exits with ERROR: Module `$abstract\vid_tilemem' is used with parameters but is not parametric!
<daveshah> Sprite_tm: remove the last synth_ecp5 line in the bugpoint script
<daveshah> And add -abc9 -top top_fpga to both remaining synth_ecp5
<daveshah> (in and out of bugpoint)
<Sprite_tm> Running, let's see what happens...
<Sprite_tm> Well, it complains it does not crash.
<Sprite_tm> Are you sure synth_ecp5 -abc9 -top top_fpga -run :map_luts;
<Sprite_tm> is supposed to run the abc9 pass?
<daveshah> No, map_luts: runs the abc9 bit and should be in the bugpoint file
<Sprite_tm> If so, I may have a Heisenbug :P
<Sprite_tm> Yep. ERROR: The provided script file and Yosys binary do not crash on this design!
<daveshah> Just to check can you post the script you are using?
<Sprite_tm> or do you mean the script I normally synth with?
<daveshah> Sprite_tm: should be `-run map_luts:` inside the bugpoint script
<Sprite_tm> Ah, derp.
<Sprite_tm> Yay, it's removing shit now.
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<mithro> daveshah: BTW Regarding your question about replacing v2x with something like nmigen which generates both the Verilog and the XML, I would be open to seeing an example and seeing if we could make it work
<daveshah> mithro: too many projects, not enough time, but I'll think about it a bit more at least
<daveshah> With a custom library, this could perhaps reduce the dependence on attributes
<daveshah> As the primary data would be in the Python code first class, but in the Verilog target might be generated as an attribute
<mithro> daveshah: It is likely we will move to a Yosys Python plugin rather than the current dependency on JSON
<daveshah> Makes sense
<mithro> daveshah: I think that might end up with nMigen being a good idea then?
<daveshah> Yes, as you could go through rtlil without any Verilog
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<pepijndevos[m]> Just throwing it out there: liberty files could also be an alternative to verilog, since it has built in timing support. Maybe not very powerful or much added value over verilog....
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<hackerfoo> I'm working on my HLS (or HLHDL?) and it's interesting how language features corespond to computer architecture.
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<hackerfoo> General recursion requires a sort of lightweight stack machine, and array access requires designing a bus.
<pie_> hackerfoo: would be interested to read a blog post on any parallels you notice there
<hackerfoo> Because there has to be a way to arbitrate access to a single RAM.
<hackerfoo> pie_ (IRC): Yeah, that would make a good article.
<pie_> wheher there's a lens through which projecting a computation yields that stuff, or something
<pie_> my ponderings about this stuff are way too vague and ungrounded to yield anything :/
<pie_> im surprised youre not in the clash channel
<pie_> though only slightly for some reason
<emily> oh, what channel is that?
<hackerfoo> I haven't gotten around to trying Clash yet, but it's interesting.