<Sprite_tm>
hackerfoo: Yes, I know it's a trick, but in this case it's unneeded. The ECP5 has perfectly good true dualport RAM, there's no need at all to duplicate the memory to get an extra read port.
<daveshah>
Yes, Yosys doesn't support true dual port RAM
<Sprite_tm>
If I didn't have a deadline to work towards, I'd try to put in support myself... as it is, I'll just bring up the ole clarity designer.
<daveshah>
Truth be told memory_bram just needs a rewrite
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<GenTooMan>
Well the ICE40 BRAM requires a synchronous clock for read write. Maybe that has been my problem? That is I can't use BRAM unless read and write are clocked.
<mwk>
hmm, so remind me
<mwk>
of the three xilinx cpld families (xc9500, coolrunner/xcr30xx, coolrunner2/xc2c*), what's the foss support status for each?
<mwk>
(well, and the fourth xc72xx/xc73xx, but I guess nobody cares about these)
<mwk>
I heard of some reverse engineering projects that should be usable?
<whitequark>
cc rqou
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<azonenberg>
mwk: xc2c32a is fully RE'd, larger xc2c are understood well enough to use but require a non-free blob
<azonenberg>
tl;dr there's a mask rom mux that you can either extract by die imaging or by copying a file from ISE
<azonenberg>
we don't have a non-copyrighted source for that mux config on the larger devices
<azonenberg>
IANAL but it may be possible to collect the data from ISE and re-format it to convey the same facts but not be a literal copy of the ISE file
<azonenberg>
rqou has a P&R tool but i don't know the status of it
<azonenberg>
xc9500 i believe is partly or mostly RE'd but no tools
<azonenberg>
and i don't know if anyone has looked at xcr30
<azonenberg>
the xc7* are untouched afaik, nobody cared
<mwk>
azonenberg: who did xc9500?
<azonenberg>
rqou did that solo i think, i dont know how far he got
<azonenberg>
xc2c was about 90% me, and rqou helped me with the last stubborn bits
<azonenberg>
but he did all of the toolchain work
<mwk>
ack, thanks
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<kc8apf>
I've got a few xc9500 boards in my library for testing tools