<mwk> kc8apf: what?
<mwk> it's not about LOUT at all
<kc8apf> doesn't debug bitstream use LOUT?
<mwk> LOUT is supported, and even if it's not due to being used in a non-serial config mode, it's ignored at worst
<mwk> I told you I suspect debug bitstreams are buggy because someone forgot to emit packet headers and basically the whole thing desyncs
<kc8apf> That wasn't my experience on 7 series nor what the docs said
<mwk> have you checked it?
<kc8apf> I didn't manually edit a debug bitstream until it works
<mwk> alright, so again, you never successfully loaded a debug bitstream on a 7series device?
<mwk> kc8apf: so FYI, I just did manually edit a debug bitstream until it works
<mwk> adding the missing FDRI packet headers does the trick, just as I suspected
<kc8apf> Huh. Interesting
<mwk> and the LOUT is silently ignored, despite me using JTAG
<kc8apf> Color me surprised that Vivado is broken and the docs are wrong
<mwk> also, I cannot see the note in ug470
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<whitequark> interesting
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<edmund> mwk: "Debug Bistream is not applicable for Zynq." https://forums.xilinx.com/t5/Other-FPGA-Architectures/ZynQ-debug-bitstream/td-p/907861
<edmund> mwk: "I was following what is written at page 233 of UG908. As that manual says, the TCL command to set the correct property to enable debug bitstreams is: set_property BITSTREAM.GENERAL.DEBUGBITSTREAM Yes [current_design]. Unfortunatly this command does not work. I think that poperty does not exist." https://forums.xilinx.com/t5/Configuration/Generate-Debug-Bitstream-for-partially-reconfigurable-designs/td-p/739329
<mwk> edmund: it's not about Zynq though, lack of debugbitstream support for Zynq is quite expected since Zynq doesn't (officially) support serial configuration modes, and debugbitstream only makes sense with those
<mwk> (although it's a lie that you cannot use it with non-serial modes; you can, it's just that the debug output won't work)
<mwk> the problem is that it emits broken bitstreams on some FPGAs where it is officially supported (Virtex 4/5/6 and Series 7)
<mwk> I've tested on a Virtex 5 board: the debug bitstream emitted by ISE indeed doesn't work (configuration fails due to CRC failure), but a fixed debug bitstream made using my tools does work (and differs from the ISE one only by adding missing packet headers)
<edmund> Is that only a problem of ISE or also of Vivado?
<mwk> no idea, I never tried emitting a debug bitstream with Vivado
<mwk> that said, the prjxray code based on reverse engineering Vivado is broken in the exact same way as ISE is
<mwk> so probably yes
<kc8apf> Vivado generates the same broken debug bitstreams
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<edmund> What woudl that debug bistreams be used for? Who (what king of developer?) would have great value from it if they would work? (Amazon F1 designers?)
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<mwk> edmund: no idea
<mwk> it's just a (crappy) debug option to be used as a diagnostic tool when shit doesn't work, and of very limitted utility tbh
<mwk> I'd say nobody missed it
<mwk> you'd have to 1) be using a serial configuration mode, 2) somehow screw it up in such a way that it sort-of works, but transfer breaks in the middle of bitstream
<mwk> oh, and it's also quite useful for the kind of developer that is reverse engineering fpga configuration and wants to learn what FAR values are valid for a given FPGA, but somehow I don't think we can make a selling point out of that
<whitequark> lmao
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<edmund> mwk: :-) I think you fully answered my question. Thank you :-D
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<gruetzkopf> hah, found a power supply that works well with the panologic things: the one from Steam Link!
<jn__> how fitting :D
<gruetzkopf> also managed to convince the xilinx mig to emit something that looks the same as the reversed pinout, now to move onto litedram
<Stary> i desoldered the jack on mine, lol
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<gruetzkopf> are you the person who tweeted about the blinky?
<gruetzkopf> (i built this https://photos.app.goo.gl/bbrte2ySNHtpHjmf9 horrible adapter)
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<freemint> Are you aware of HDL called sfl?
<whitequark> i've encountered it
<freemint> Is it unsuited for your puposes too? If so why?
<whitequark> it's not open-source for one
<whitequark> i think you can't even get the binaries for it
<whitequark> other than that it looks pretty good
<freemint> I could look into getting binaries for it but not open source is a big -
<whitequark> it might also be patented
<freemint> From the age it looks more like it might be out of patent but i see why a clean room approach has it's benefits
<freemint> Although if you make a design from scratch you got to be carefull not to accidentally implement something they have a patent for.
<daveshah> Or one could just not care about patents...
<freemint> The boomers are still in power ... so they make you care
<whitequark> patent holders first against the wall
<daveshah> I wouldn't be surprised if Yosys and nextpnr violated at least a dozen patents
<whitequark> which is why i'm glad i won't be the one hit with a gratuitous lawsuit
<daveshah> If you worry about patents you might as well just give up trying to do EDA
<jn__> patents are so ridiculous that i don't think individuals can afford to worry about them
<whitequark> it's not that
<whitequark> it's that if you reimplement something patented good luck getting debian to ship it for example
<daveshah> But tbh how do you even know if you are implementing something patented
<daveshah> there are so many patents all so vaguely worded
<whitequark> oh what i mean is from looking at how SFL is developed, i don't expect the authors to be particularly friendly
<whitequark> to reimplementation
<whitequark> do i want to put years of my life into that? no.
<freemint> whitequark, i do not suggest that. Currently the software running sfl has gone into get a license by becomming member in our association or 50$ a year mode although is it dubious if the PARTHEON study group is still around.
<freemint> oh there is even a free membership
<whitequark> ok so if i can't redistribute it i can't use it for my projects like Glasgow
<freemint> yeah it does not make sense from that point of view
<daveshah> Reminds me of LegUp, which they even have the cheek to call "open source" (despite having a license that prevents redistribution, iirc)
<freemint> Going through the effort to reimplement something existing becomes only interesting if it is fully out of patent.
<whitequark> more like if the original implementer isn't hostile
<whitequark> or if it differs sufficiently
<freemint> that can work too.
<freemint> but not being hostile can flip into hostile. Out of patent not :)
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<whitequark> true
<freemint> mhh the organization behing PARTHEON seems to be dead for 10 years, 15 years ago it became "indepent" from the company (read it lost interest) . SFL also seems to older than VHDL or "Verilog-HDL" by half a decade. Partheon was created around 1990. I also ping them to see if they are still alive. If i learn anything interesting i tell you.
<whitequark> huh
<whitequark> interesting
<whitequark> so it's an improvement on its successors
<freemint> yeah that is what i though
<whitequark> how unsurprising
<freemint> Would it be worth digitizing and translating japanese technical documents if they just said "yeah you can have it"?
<whitequark> it would be certainly interesting to me, i study languages quite a bit
<whitequark> which is generally advisable when you're designing one
<freemint> http://www.parthenon-society.com/archive/NTT/slide/eng/sld_e6.htm Would a behavorial/procedural single phase synchronous language even be interesting?
<whitequark> yes, it has some built-in pipelining stuff
<whitequark> i want to understand how that works exactly
<freemint> Is Netlist a standardized format?
<whitequark> no
<whitequark> "netlist" is like "source code"
<whitequark> or really "object file"
<whitequark> it's a , well, net list.
<whitequark> list of connections.
<whitequark> there's tons of formats
<freemint> that sucks
<hackerfoo> whitequark: What language are you designing?
<whitequark> hackerfoo: nmigen
<whitequark> well, i'm more refreshing it
<whitequark> there's still language design involved but i'm not doing it from scratch
* ZirconiumX wonders if there will be a nnmigen
<whitequark> unlikely
<freemint> When do you want a language that can do asynchronous stuff?
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<whitequark> like asynchronous logic?
<whitequark> that's not me that's emily
<emily> I like how you're giving me a reputation for self-timed logic when I know approximately nothing about it
<freemint> VHDL and verilog both "support" asynchronous logic, when do you really need that feature?
<whitequark> define asynchronous logic
<freemint> Logic that operate by local negotiations rather than under the control of a global clock ?
<whitequark> right, so, VHDL and Verilog synthesizers don't support it, and the languages don't really support it either
<whitequark> you can instantiate it. you can instantiate it in nmigen also if you really insist on that
<freemint> What does "instantiate" mean?
<whitequark> async_thing u1 (.i(i), .o(o));
<whitequark> treat them as blackboxes
<freemint> Is it similar to declaring in C?
<whitequark> no
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<freemint> ah since VHDL and Verilog do not really have support for it (on the affordable end) lacking them is a good tradeoff if it makes the language easier and the simulations faster?
<whitequark> i'm not sure what you mean by that
<whitequark> nmigen specifically targets synchronous logic, because vhdl and verilog support neither very well
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<freemint> ok , sorry i will learn more about HDLs and rephrase that question more intelligently when i am better
<hackerfoo> Verilog supports async logic, but I couldn't get any to work on an FPGA, so you'd need to be designing an ASIC.
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<daveshah> That's more down to the synthesisers and PnR tools being broken as much as anything else
<daveshah> Async logic is definitely possible in FPGAs, there have been papers in the past.
<daveshah> How useful it is in current commercially available FPGAs is more up for dispute
<hackerfoo> I settled with breaking loops with registers, but the first iteration falls through to avoid a bubble, so it's not entirely synchronous.
<hackerfoo> You'll generally need to do this anyway. I think locally sync, globally async is probably a better approach.
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<hackerfoo> Just because you'll spend a lot of resources to make the whole thing async.
<hackerfoo> At least in an FPGA.
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<TD-Linux> speaking of patents, exfat is in the open innovation network now. so maybe people will actually use it
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<emily> TD-Linux: so last time I heard about this it was kind of useless for free software that isn't a specific version of linux?
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<emily> like they list "exactly these things can use these patents" and it does not include the right to unrestricted forks or whatever
<emily> seems more like bigcos trying to use patents to keep linux ahead now that it's won and they've given up on trying to use patents to kill them
<emily> *to kill it
<ZirconiumX> If only Oracle relicensed ZFS...
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<TD-Linux> emily, it is not perfect, in particular
<TD-Linux> “Linux System” shall mean a Linux Environment Component or any combination of such components to the extent each such component is (i) generally available under an Open Source License or in the public domain (and the source code for such component is generally available) and (ii) Distributed with, or for use with, the Linux Kernel (or is the Linux Kernel).
<TD-Linux> so yeah doesn't help with embedded implementations :(
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<emily> ZirconiumX: I wish :(
<emily> I avoided ZoL for the longest time for licensing reasons but it's going to be a while before bcachefs is a thing...
<emily> TD-Linux: right so it protects linux at the expense of BSDs and other Free OSes
<emily> which i think is pretty crappy tbh
<TD-Linux> emily, it's a defensive license so having a limited scope is important
<TD-Linux> but yeah I'd rather a scope limited to exFAT rather than a scope limited to linux :(
<emily> well maybe if they really wanted to be nice about their patents they would just let anyone use them :V
<emily> hard to find it too satisfying when they grant limited licenses when for the most part they shouldn't have the IP in the first place (or at all depending on your opinion of software patents)
<TD-Linux> software patents should be deleted
<TD-Linux> er
<TD-Linux> patents should be deleted
<TD-Linux> defensive licenses are a hack around a broken system. I think they are useful but they have to be written very carefully
<ZirconiumX> I think EU law doesn't recognise software patents, but I am *not* a lawyer
<TD-Linux> unfortunately it does
<TD-Linux> one of the biggest H.264 lawsuits was in germany
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<flyback> hp's patent on serial redirect of console expired *today*
<flyback> btw
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<hackerfoo> US law also doesn't recognize software patents: https://en.wikipedia.org/wiki/Software_patents_under_United_States_patent_law
<hackerfoo> Which is why US software patents start with some mention of a machine.
<emily> that seems like an overly generous way of putting it
<hackerfoo> It's pretty stupid that they allow that loophole even when it seems to go directly against the intent.
<emily> "In DDR Holdings v. Hotels.com,[31] the Federal Circuit upheld one patent and invalidated several others under Alice. This is the only instance since the Alice decision in which the Federal Circuit held a patent to be eligible. The court said that the eligible patent solved an Internet-centric problem in an inventive way. (It essentially framed one website within another, so that it appeared to be a part of the other
<emily> site.)"
<emily> how inventive ~
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<hackerfoo> It's inventive to add features back that have been intentionally removed? I guess rooting is inventive, then.
<emily> pretty sure that (i)frames weren't even deprecated at the time :)
<hackerfoo> Oh, nevermind, <frameset> was removed, not <iframe>.
<emily> though it seems to be a server-side amalgamator rather than a client-side one? who can tell, patent language is such nonsense
<hackerfoo> Still, super inventive. I think they should mix in a bunch of fake ridiculous patent cases to prove that the courts have some idea of what they are doing.
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<hackerfoo> If you win a fake patent case, you get a free pass.
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