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<whitequark>
mwk: ha, i found a board with xc3s and xcf04s
<whitequark>
not even -e i think
<whitequark>
mwk: >The XCFxxP JTAG TAP pause states are not fully compliant with the JTAG 1149.1 specification. If a temporary pause of a JTAG shift operation is required, then stop the JTAG TCK clock and maintain the JTAG TAP within the JTAG Shift-IR or Shift-DR TAP state. Do not transition the XCFxxP JTAG TAP through the JTAG Pause-IR or Pause-DR TAP state to temporarily pause a JTAG shift operation.
<whitequark>
but... why
<mwk>
umm, hardware bug?
<whitequark>
yeah but like, why
<whitequark>
i guess you don't know
<whitequark>
anyway uh, i'm not sure how to power this thing
<whitequark>
it powers off PCI but only actually pushes data through SATA
<whitequark>
except it's a xc3s so it doesn't have serdes so it uses a SATA-to-IDE bridge
<mwk>
it what
<whitequark>
bonus points for guessing what it is
<whitequark>
a huuuuuuge card
<whitequark>
there's not much on it other than: SATA connector, XC3S, configuration logic, button, LEDs, [redacted] and some other large connectors
<mwk>
but but but
<whitequark>
and an LDO on the back that was so overloaded the board yellowed around it
<whitequark>
3A rated.
<mwk>
please tell me that at least the board is an ATA/SATA host
<whitequark>
it is not.
<whitequark>
what it is is very, very cursed.
<mwk>
I... have no idea
<whitequark>
hint: if i said what [redacted] is it would narrow it down to 1, maybe 2 classes of devices.
<whitequark>
and that component is extremely unusual.
<mwk>
so it pretends to be a storage device
<mwk>
it's not a SATA-to-iSCSI bridge?
<whitequark>
far more cursed
<mwk>
that would be too simple, yes
<whitequark>
hint#2: it has to be huge.
<whitequark>
like "top of the line video card" huge
<whitequark>
no fans or heatsinks though
<whitequark>
i think it might be the largest PCI device i've ever held in my hands
<whitequark>
although it's not quite as long as those enormous ISA/VLB cards with tons of discrete logic
<mwk>
hmm
<whitequark>
and of course it's not a prototype but a mass product of some sort, although somewhat niche
<mwk>
a reader of some obscure media?
<mwk>
but, other large connectors...
<whitequark>
to be honest, i have no fucking idea what the button does or why would one even put a button on this board
<whitequark>
*looks in the manual* oh. i ... see
<whitequark>
well that's cursed.
<kc8apf>
SATA DRAM
<mwk>
oh.
<whitequark>
correct. SATA DDR1 card, Gigabyte GC-RAMDISK
<mwk>
oh.
<whitequark>
with a huge lithium battery.
<whitequark>
and four slots
<mwk>
it... a PCI SSD
<mwk>
sort of
<whitequark>
not ... not PCI
<whitequark>
moreof a SATA SSD
<whitequark>
except it sucked
<whitequark>
it sucked so much, it couldn't saturate the SATA-IDE converter it used
<whitequark>
like, from the IDE side
<kc8apf>
those were popular for a while. Just not that _particular_ device
<whitequark>
lol
<whitequark>
and the button is a battery level indicator
<mwk>
how do you even do that
<whitequark>
do what
<sorear>
with a battery even, nice
<mwk>
not saturate IDE
<whitequark>
oh. lol
<mwk>
given DDR memory
<kc8apf>
implement IDE naively
<whitequark>
given *four slots* of DDR memory
<kc8apf>
wait for the full command to come in before starting RAS
<sorear>
pio only?
<whitequark>
lol
<kc8apf>
probably
<whitequark>
wait. what. are you serious
<whitequark>
who the fuck would make a pio only ata device
* cr1901_modern
sheepishly raises his hand
<kc8apf>
that would definitely get you in the space of having such terrible latency you can't saturate IDE
<whitequark>
lol
<whitequark>
kc8apf: i think it sort of came close but not really
<whitequark>
like 80% that?
<kc8apf>
oh, UDMA then
<sorear>
_Iām_ joking. I suspect kc8apf may not be.
<cr1901_modern>
>an integrated battery allows the contents of DRAM to be preserved for a limited amount of time after the device's power supply is interrupted
<cr1901_modern>
This is not very reassuring.
<whitequark>
>Please note that data in i-RAM is not covered under the warranty.
<kc8apf>
I've seen terrible things
<whitequark>
>For users who wish to install operating system in i-RAM, please prepare the minimum free harddisk space for the operating system.
<sorear>
board may come with defective data in i-RAM
<kc8apf>
I bet it'd saturate the link with large sequential reads
<whitequark>
i'm not gonna plug it in
<whitequark>
ok fine
<whitequark>
i might plug it in
<kc8apf>
I prefer to have my OS vaporize on power loss
<whitequark>
wait. where the fuck am i going to get DDR RAM
<cr1901_modern>
I have some
<cr1901_modern>
And well, Staples (do they have those in RU) used to sell it for a while
<whitequark>
no they do not
<mwk>
I just got DDR RAM from ebay whenever I needed some
<whitequark>
... DDR RAM *and* a PCI slot
<kc8apf>
power in PCI slot form
<mwk>
(which ummm has ben a worrying amount of times)
<sorear>
are these like, DDR1 socketed DIPs?
<kc8apf>
nah, DIMMs
<whitequark>
uhhh
<whitequark>
my raccoon roommate just pulled a motherboard with two populated slots of DDR1 ... somewhere
<kc8apf>
haha
<mwk>
awesome
<whitequark>
i have a SATA-USB adapter but the board has a capacitor where the adapter has SATA power
<whitequark>
i can probably just desolder it
<whitequark>
who tf cares
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<whitequark>
i didn't have a sata cable that would work with this but i did have an usb sata converter
<whitequark>
oh. i said that part already
<whitequark>
yeah
<whitequark>
it looks seriously cursed
<whitequark>
now power...
<whitequark>
uhhhh it uses... +12 and +3.3
<whitequark>
i think?
<whitequark>
yeah
<whitequark>
+5 isn't connected
<whitequark>
... why would they drop like 10 volts on that poor LDO
<sorear>
sometimes one gets the impression switching regulators were invented around 2005
<whitequark>
you know what, i'm not even going to bother tracing the rest of it
<whitequark>
it's clearly cursed
<whitequark>
i'll just take the CPU out of that motherboard and use my micro ATX supply to power it
<whitequark>
for that additional, extra cursed factor
<whitequark>
(maybe something else for several words)
<zignig>
.alloc will give me a block of writeable addresses.
<zignig>
I spent two hours fixing a JR vs JSL, <facepalm>
<zignig>
*JAL
<whitequark>
is the difference just that it doesn't require you to type several .word directives?
<zignig>
yes.
* zignig
speculates wildly.
<whitequark>
ahh ok, so i was going to make something like
<whitequark>
leds: .zero 1
<whitequark>
so you always declare a label with the label syntax.
<zignig>
I want a python program that drops me into a boneless console that I can automagically build any Elaboratable and hand me back an ASM driver for IO
<zignig>
I'
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<zignig>
I have a warmboot , need a reset and a flash device that will split images and "user data" that I can R/W from boneless-v3
<zignig>
That way configuring my tinbx becomes a interactive text interface, "pin13-16 !video" , or if valentyusb gets ported i becomes ": bob2 !usb serial_port ; , and 12 seconds later gateware.
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<mkdir>
how do i see the waveform in iverilog
<mkdir>
how do i use it actually lol - I can't find great resources
<zignig>
mkdir: o/
<mkdir>
hi zignig
<zignig>
are you writing in nMigen or <smelly>verilog</smelly>
<mkdir>
verilog lol
<whitequark>
gtkwave lets you view the waveform iverilog saved
<zignig>
from reading back log , you are trying to get data points off <biteme/arrrrgh>DEVICE</close>
<zignig>
best way to view wave forms (linux) is gtkwave you need a vcd file as input.
<mkdir>
how about mac?
<mkdir>
verilator has it built in right/
<mkdir>
are there any good docs for verilator?
<mkdir>
i mean
<mkdir>
iverilog
<zignig>
doc? pfft , this is open source , RTSC ;)
<zignig>
whitequark: the goal is to have a slip link that gives me 256 dewvices, attach to _zero_ console and you can ask for _whatever_ gateware you need. shazam.
<mkdir>
lol zignig
<mkdir>
I found Scansion
<mkdir>
hmm.. can't really even use this iverilog on my mac
<mkdir>
zignig what is a simulator used for if not for waveforms?
<mkdir>
waveform view
<mkdir>
jw
<Sprite_tm>
mkdir: depends; I have a Verilator sim of my entire soc that I can throw gdb at (gdbstub on soc, emulated serial port via pty). Works nicely to inspect sw issues.
<Sprite_tm>
Also, it's 'only' 400x slower than real hardware :P
<sorear>
400x slower than fpga?
<mkdir>
Sprite_tm hmm I see
<tnt>
400x is pretty good
<Sprite_tm>
Agreed :) Still gives me seconds-per-frame on the lcd emu screen, but hey :P
<Sprite_tm>
Kinda wondering if I can quicken things by splitting the design into multiple parts, each with their own thread, syncing up each clock tick... but that sounds like lots of effort :P
<zignig>
mkdir: currently I am making nmigen so when I run a "simulaton" it drop a .vcd into the working directory. IFF my console is local I can view the signals.
<zignig>
mkdir: what are you building with your icestick?
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<X-Scale>
Sprite_tm: consider yourself lucky. You made me remember this tidbit of MIPS' ancient history:
<X-Scale>
Sprite_tm: "They booted the Unix operating system on the R4000 RTL model about six months before Mips gave the design to its manufacturing partners. It took a 50-MIPS Mips 6280 seven days of processing to reach the Unix prompt" from "The Mips R4000 Microprocessor" back in 1992
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<mkdir>
zignig: I'm putting together a clock divider circuit
<mkdir>
and I wanna see the simulation of the signal changing
<marcan>
looking at the iCE5LP1K, I see the iCE5LP4K is supported. any idea whether that's the same die or how difficult it would be to add support for u1k?
<tnt>
marcan: it's the same die
<marcan>
oh cool
<tnt>
smae config file size
<marcan>
so it should "just work" modulo IO mapping?
<marcan>
(how do they stop you from just using it as a 4k?)
<tnt>
icecube ?
<marcan>
nah, making a board
<marcan>
oh you mean their software
<tnt>
yes.
<marcan>
heh
<tnt>
it's a sw limit when you select that device.
<marcan>
lol
<tnt>
The IOs are the same also AFAICT.
<marcan>
I see
<marcan>
I guess I'll go with that then
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<whitequark>
hm, need to add support for that to nmigen
<marcan>
that would be nice
<whitequark>
oh it's already there
<marcan>
lol
<whitequark>
aaaalmost
<marcan>
I was going to say I'm fine with verilog since this is such a trivial application
<marcan>
but hey, if I can use nmigen with zero effort I will
<marcan>
:p
<whitequark>
marcan: you need to add a package disambiguator to u4k i think
<whitequark>
or ...
<whitequark>
oh it's the same package for lp1k and lp4k?
<marcan>
yeah
<whitequark>
it's *literally the same fucking chip?*
<marcan>
same 3 options
<marcan>
apparently
<marcan>
I guess they fuse something in at least?
<marcan>
I assume at least the ID it returns is different
<marcan>
otherwise, lol
<tnt>
returns ?
<whitequark>
marcan: pushed support for lp1k
<tnt>
I'm not even sure you can read an ID.
<whitequark>
and yeah i dont think ice40 has id
<marcan>
lol.
<marcan>
amazing
<marcan>
I guess hypothetically they can sell chips with some broken 3/4 of logic blocks (as long as the same fixed 1/4 is always good)
<marcan>
but lol
<whitequark>
nope
<whitequark>
they dont restrict placement
<marcan>
lol.
<whitequark>
and the yields arent that low i assume anyway
<marcan>
so it's literally an "if blocks > limit for smaller device, lol error out" in their software?
<whitequark>
yes
<marcan>
amazing
<whitequark>
xilinx does this too for smaller artix
<whitequark>
it's interesting because you're routing limited there often
<whitequark>
and that means you can push it further than it should be possible on a device that size
<whitequark>
cuz it only limits placer, not router
<marcan>
yeah but then there's *literally no reason* to ever buy the more expensive chips
<marcan>
you're paying for a laser marking
<whitequark>
yes
<tnt>
marcan: if you look at the table https://www.latticesemi.com/Products/FPGAandCPLD/iCE40Ultra.aspx you will see that the bigger one has "PWM" as "No". That's literally because that PWM IP is implemented in the extra fabric by the sw ... (and for the large device, there is no extra fabric)
<marcan>
hahahahahahahahahahahaha
<whitequark>
incredible
<marcan>
tell me they literally have a pwm.v somewhere in there
<tnt>
I'm wondering if the fomu guys are using the up3k chip.
<tnt>
marcan: yeah
<marcan>
amazing
<whitequark>
oh yeah i should add that to nmigen too
<marcan>
I have a fomu somewhere
<sensille>
wait, do they also do that for ecp5?
<whitequark>
yes
<tnt>
marcan: even the hard IP like SPI have actual synthesizable verilog (even if they are truly hard IP) shipped with the sw. Which is actually useful to understand how they really work and what the "reserved" bits do.
<marcan>
hah, that's neat
<marcan>
(not sure if I mentioned that time I had to decrypt the lattice ecp3 pcie core to hack in a change...)
<marcan>
(their crypto is... not amazingly hard to defeat)
<marcan>
(and then you get commented verilog output, lol)
<whitequark>
you can usually just gdb vendor tools
<whitequark>
they dont try that hard
<marcan>
so their 64-bit build literally had an rsa_key symbol.
<sensille>
how many different chips to they have for ecp5? or really all just one?
<marcan>
obfuscated by "xor every byte with a constant".
<tnt>
sensille: look at the size of the configuration bitstreams.
<tnt>
that usually gives it aways how many real dies there are.
<sensille>
great
<daveshah>
The real dies are 25k, 45k and 85k
<daveshah>
all with SERDES
<tnt>
marcan: sometimes I wonder if the dev don't do it "on purpose" just to be nice but in such a way that can still pass off as an error.
<whitequark>
marcan: oh, remember that xilinx ise's shipped broken flexlm for years
<whitequark>
like, cryptographically broken
<whitequark>
the authors of the paper contacted xilinx
<whitequark>
and got told "if someone wants ise that much they can have it" moreor less
<whitequark>
for years after the paper got published...
<whitequark>
you could get their master key from just an ise install or something
<daveshah>
Xilinx et al make very little money on Vivado licenses
<daveshah>
They are mostly a way of avoiding a support burden for bigger devices/complex features by companies that won't buy many parts
<whitequark>
they spend a token effort tracking down piracy
<daveshah>
FWIW, Lattice didn't even bother to device lock the free license they give away with eval kits
<daveshah>
So it's 100% identical to the one that costs $1000
<tnt>
I know when I worked for an IP design company, Xilinx was basically giving licenses aways.
<daveshah>
with the cheapest dev kit including one being $100...
<whitequark>
pretty sure they do that on purpose
<whitequark>
although... being lattice... no, not sure
<daveshah>
They claim somewhere it is device locked
<daveshah>
But it's so device un-locked that it even works for ECP fucking 4 if you use it with Diamond 2.0
<whitequark>
lol
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<daveshah>
Actually, they don't say it is device locked, I misread
<daveshah>
> that enables design for the LFE5UM5G-85F FPGA featured on the ECP5 Evaluation Board
<marcan>
lol
<daveshah>
doesn't actually imply device locking, as it doesn't say anything about other FPGAs
<marcan>
nice.
<whitequark>
lattice probably licenses the tool ip at a fixed cost or something, right
<marcan>
also the whole "eval cores time out after 30 minutes or whatever"
<marcan>
surely that's, like, a bit in the bitstream?
<daveshah>
I believe Synplify is a per-install cost
<whitequark>
oh right
<daveshah>
That is why even the free Diamond is MAC locked
<daveshah>
And that weird tickbox about not being a Mentor Graphics employee etc
<marcan>
speaking of that MAC locking
<marcan>
it picked up my virtual ethernet adapter MAC
<marcan>
which is the same everywhere
<marcan>
so much for MAC locking
<whitequark>
i installed ise a few days ago and it ardently insisted on looking at eth0
<marcan>
like some tun thing or something
<whitequark>
so i made a eth0 with a mac 020000000000
<marcan>
IIRC their list of ethernet interfaces is hardcoded?
<marcan>
and it couldn't find mine or something?
<marcan>
I think
<whitequark>
actually, what it did is it tried to load glib-dbus (why?!) and segfaulted
<marcan>
lol
<daveshah>
Yep, same with icecube
<marcan>
I also have an LD_PRELOAD somewhere to just make it always use the same MAC
<whitequark>
also i think the actual ise tools aren;t actually properly mac locked
<whitequark>
because i don't even have that eth0 anymore
<mumptai_>
out of curiosity, is there any ANN inference engine in the open source domain that isn't tied to some proprietary toolchain (like vivado HLS)?
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<tnt>
Oh FFS ... I've been wondering why my design was behaving weirdly ... turns out I had forgotten I had hacked up a SB_WARMBOOT block at the same address as the gpio register I just added ...
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* genii
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<TD-Linux>
daveshah, ise always looks for eth0. and if eth0 isn't there it just uses all zeros
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