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<pb7>
hayo~
<pb7>
trying to build ecp5 tools and `make` examples, have two bugs:
<pb7>
first one is "KeyError: 'MULT18X18D_REGS_ALL'" from trellis_import.py:172 when building chipdb (reverting to old db revision fixes things)
<pb7>
another is "Found netlist using legacy-style JSON parameter values, please update your Yosys." when trying to build examples.
<pb7>
is it me being stupid or should i fill issues?
<pb7>
(everthing from git masters, will try releases now)
<daveshah>
1. Right now you need to use the git submodule version of database not prjtrellis-db master
<daveshah>
2. Which example? Are you sure Yosys and nextpnr are up to date?
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<ZirconiumX>
RiP
<ZirconiumX>
How does one compare two .vcd files for equality, i.e. that the data within them is identical?
<ZirconiumX>
I want to compare the simulation output of the original input RTL with the output of the RTL after synthesis to check that synthesis hasn't broken the code somehow
* mwk
would recommend using equivalence checking instead
<daveshah>
Equivalence checking isn't perfect, comparing vcds is a very valid approach
<ZirconiumX>
I'd err on the side of caution and have both :P
<daveshah>
(anything with a big multiply in will probably kill any of the equiv checking options in Yosys at least)
<daveshah>
Personally though, I'd create a miter module that instantiates the pre and post sim models and sets a flag (e.g. in the return code or a file) if the outputs diverge
<daveshah>
*pre and post synth
<ZirconiumX>
Okay, that sounds like a reasonable approach
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<pb7>
it was me being stupid; week-old yosys; forgot to update local mirror
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