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<ZirconiumX>
Ugh, implementing fixed-point division is pain
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<emily>
"It also means that the PS2 can handle a lot more sophisticated Artificial Intelligence programming so that you have intelligent human-like opponents. And with a floating point calculation performance of 6.2GFLOPS/second, the overall calculation performance of this new CPU matches that of a super computer." hehe, some things never change
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<ZirconiumX>
emily: I mean, they were so eager about it they called the processor the "Emotion Engine" because it was supposedly good enough to produce games with facial reactions
<ZirconiumX>
The PS2 was a wacky architecture, but it was honed to a fine edge by '04
<implr>
shame every console is now either amd x86 or a tegra
<implr>
it certainly makes gamedevs happy
<implr>
but weird architectures were cool
<ZirconiumX>
I found the challenges of the PS2 to be fun to work with
<ZirconiumX>
But all the NES/SNES devs say I'm spoiled
<emily>
can't wait for the Xbox Zero to use a Mill CPU
<ZirconiumX>
The Mill seems interesting, but I'm doubtful it'll ever be anything other than vapourware and patent lawsuits.
<whitequark>
xxxbox
<emily>
the Mill seems like half a mix of good but difficult ideas and half just completely random stuff they made up to be different from anyone else
<emily>
though that's my impression as someone far from remotely competent about microarchitecture design
<whitequark>
which would you say are good but difficult ideas
<emily>
I sort of dislike mutable registers as a model so the belt machine stuff is interesting to me
<whitequark>
the belt machine is a very simple concept
<emily>
by difficult I mean like, potentially difficult to make work in practice
<whitequark>
in a way, it's simpler than having registers
<whitequark>
oh, you mean in the toolchain?
<emily>
I guess? I meant more generally like, "difficult to make work well in all the things you need for a fully-functioning practical CPU architecture"
<emily>
but again, that's my completely-unqualified opinion
<ZirconiumX>
To me the biggest question is bootstrapping. Imagine a motherboard vendor having to recompile their BIOS to run on any possible plugged in chip
<whitequark>
just stick a risc-v core there to do it
<ZirconiumX>
Or else the chip has to be soldered on
* emily
is very interested in inherently-parallel graph-reduction machines
<whitequark>
emily: the benefit of the belt machine is that you throw out register renaming
<whitequark>
it's one less layer on top of an existing CPU
<implr>
stealing the not-a-thing bit from itanium also seems good
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<pie_>
anyone know where to get a (cheap) spartan 3AN starter kit? i owe the university one and it has disappeared due to circumstances
<pie_>
well, i only really need the board i think, i have the box and stuff
<ZirconiumX>
Ouch
<ZirconiumX>
S3 is pretty old
<pie_>
yeah lol, welcome to post soviet countryÜ
<pie_>
?
<pie_>
the prof might not even care that nuch but i feel bad about it
<whitequark>
can you just pay them
<whitequark>
wait, if you're saying postsoviet, try starterkit.ru
<whitequark>
they sell some relatively cheap 3a crap
<pie_>
starterkit oesnt go through google translate for some reason. well, i guess ill just ask what to do about that kit
<Xark>
implr: As a game developer I miss PowerPC and CELL (however, you are correct publishers don't miss those much). :)
<Xark>
^ and MIPS even. :)
<pie_>
man i need to set up a bouncer, im about to drop off again, bbl
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<ZirconiumX>
Xark: I like MIPS, but others here are a lot less keen on it
<tpw_rules>
i know this isn't cool kids club risc, but ARM Is nice
<ZirconiumX>
I haven't used ARM much. I know ARM32 has quirks of its own
<tpw_rules>
neon is nice too
<ZirconiumX>
Like how it exposed the pipeline of the original cores resulting in writes to PC doing wacky things
<tpw_rules>
i had to hand-code a couple of routines
<tpw_rules>
also itt
<tpw_rules>
i had to learn mips in school and didn't really get excited. maybe the lots of registers
<tpw_rules>
in comparison i still don't know x86 asm
<ZirconiumX>
Probably for the best
<ZirconiumX>
tpw_rules: lots of registers is a good thing IMO
<tpw_rules>
yes
<tpw_rules>
it is
<tpw_rules>
arm doesn't really have that many and they're pretty special purpose and constrained by calling convention anyway
<ZirconiumX>
Compare MIPS' 31 GPRs plus constant zero to x86's 7 plus stack register
<ZirconiumX>
(obviously, x86-64 helped a lot there)
<tpw_rules>
like between mips and x86 i would say arm is 2/3 x86 1/3 mips
<tpw_rules>
in terms of general register file weirdness
<ZirconiumX>
POWER is also kinda weird
<Xark>
ARM is okay, but not my favorite. The mostly wasted conditional bits and issues with immediates come to mind. NEON is "cool" but is pretty slow (at least on the Cortex-A7 I cared about - PS2 VU seemed much faster [in cycles at least]).
<tpw_rules>
yeah it's not fast
<tpw_rules>
but it's pleasant :P
<ZirconiumX>
32 registers but r0 does a lot of weird things
<Xark>
tpw_rules: Agreed. :)
<ZirconiumX>
Xark: oh man, the VUs...
<tpw_rules>
also i saw something on i think one of fabian giesen's blogs about in his experience the powerpc in the wii would run "random game logic" as fast as the powerpcs in the xbox 360 and ps3
<tpw_rules>
since the former was out of order, even though it was clocked at like 1/5 the speed
<Xark>
ZirconiumX: I wish the assembler enforced r0 vs 0, but I thought using the "register order" in opcode to determins constant 0 vs r0 was semi-clever.
<ZirconiumX>
tpw_rules: oh yeah, the Wii's chip traces its heritage to the PowerPC G3
<tpw_rules>
ah, power macs
<Xark>
ZirconiumX: With the assembler "unreliable" it wasn't great if you weren't paying close attention.
<ZirconiumX>
Xark: did you ever use the SuperH in the Dreamcast?
<tpw_rules>
i did a bunch of reverse engineering on an SH3 once
<tpw_rules>
sh3 seems weird
<ZirconiumX>
SuperH is very weird :P
<ZirconiumX>
tpw_rules: and you can tell because it was weird enough for ARM to license as the base of Thumb
<tpw_rules>
yeah i think i heard that from raymond chen?
<ZirconiumX>
Yup
<tpw_rules>
at least ARM doesn't have delay slots
<Xark>
ZirconiumX: I did, but only a few titles. I didn't do a lot of asm on it, but I recall Super-H reminded me of a wacky enhanced 68000.
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<ZirconiumX>
tpw_rules: I have learned to love the branch delay slot
<ZirconiumX>
Even if someone put three branch instructions directly next to each other in actual production code
<tpw_rules>
this is illegal, you know
<ZirconiumX>
It's legal MIPS
<ZirconiumX>
Stupid MIPS but legal
<tpw_rules>
it's defined?
<ZirconiumX>
Yes
<tpw_rules>
to do what
<tpw_rules>
well what do you mean by "next"
<tpw_rules>
like in each others delay slots?
<ZirconiumX>
Yes
<tpw_rules>
according to raymond chen again it's unpredictable
<tpw_rules>
what does it do
<ZirconiumX>
if you have b A; b B then the processor will execute the first instruction of A and then jump to B
<tpw_rules>
and that's actually defined?
<ZirconiumX>
Yep. Not at all recommended, but defined.
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<tpw_rules>
i don't believe you
<ZirconiumX>
This is at least what the MIPS chips in the PS1 and PS2 do
<ZirconiumX>
I haven't experimented with any other, but that is what those chips do.
<tpw_rules>
i mean it's what they do, yes
<tpw_rules>
i knew that
<tpw_rules>
but i find it hard to believe the manual says you can do it
<ZirconiumX>
tpw_rules: "The following sequences should not be issued: Branch-Branch; Branch-ERET"
<tpw_rules>
ok so yes it is undefined
<tpw_rules>
or illegal or whatever
<tpw_rules>
anyway chen says it will do what you said, unless you take an exception or interrupt
<tpw_rules>
but i think that's kind of hard on ps1/2 so it probably basically never happende
<ZirconiumX>
The SH4 has a "slot illegal exception" to prevent a branch in a branch delay slot
<tpw_rules>
that also seemed silly
<ZirconiumX>
It seems saner to me
<tpw_rules>
well i more meant the specific exception type
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<GenTooMan>
hmm how does one use special features of an FPGA such as a PLL in nmigen and migen? Also adding a clock domain in nmigen isn't obvious how to do. the <object>.d appears to be a reference to <object>.domains suggestions welcome clues especially. migen has some information regarding clock domains in it's doc but I am using nmigen. There are no docs for nmigen (WIP hopefully).
<adamgreig>
use Instance() to add some specific thing like a pll
<adamgreig>
in nmigen
<GenTooMan>
let me check that out and thanks for the direction.
<adamgreig>
assign to members of m.domains to add a clock domain, e.g. `m.domains.slow = ClockDomain("slow", reset_less=True)`, or append to m.domains, e.g. `m.domains += ClockDomain(...)"`