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<freeemint> Are you aware of a cheap (< $120) FPGA that can be plugged into PCI-(E) has atleast 100k LUTs and is programmable with free (as in beer) software?
<freeemint> well i actually do not need that many LUTs
<promach> freeemint: would https://www.crowdsupply.com/alphamax/netv2 be suitable for you ?
<freeemint> promach, that looks really interesting. I keep an eye on it. Slightly more expensive and less powerfull than i would want but it seems fair compared to the other boards.
<hackerfoo> freeemint: This is more expensive, but has 215k LUTs, 1GB RAM, and 4x PCIe: https://www.crowdsupply.com/rhs-research/nitefury
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<hackerfoo> Oh, wait, 512MB. Still more than this: https://numato.com/product/aller-artix-7-m-2-fpga-module
<hackerfoo> And if you're lucky, -3 speed grade.
<hackerfoo> I got mine about a week ago.
<freeemint> really interesting looks like a good option too. Hackerfoo how necessary is external cooling?
<hackerfoo> freeemint: Very
<hackerfoo> The fan rotor on mine was glued in place due to a silly assembly mistake, and it hit 140 degrees C with the example project.
<freeemint> mhh then i will look a bit more. My orginal plan was to not longer have a dev board flying around but inside a laptop cooling externally is hard ....
<hackerfoo> I talked to Dave about it, and the new ones shouldn't have that problem.
<freeemint> Where did you plug in the active cooling power connector?
<hackerfoo> You also might want a JTAG debugger, but in theory you could bootstrap across PCIe.
<hackerfoo> It has it's own fan.
<promach> hackerfoo: what do you mean by "bootstrap across PCIe" ?
<hackerfoo> I don't expect this to work in all but the bulkiest laptops. This is a Hades Canyon NUC.
<hackerfoo> Send the bitstream over PCIe and use partial reconfiguration.
<promach> hackerfoo: and how would you debug your design without JTAG debugger ?
<whitequark> you normally debug a design on an FPGA with an I
<whitequark> LA, no, no?
<whitequark> ugh, awful connecion
<promach> whitequark: ILA requires JTAG debugger connection
<whitequark> ot really
<whitequark> *not really
<promach> ??
<whitequark> why would it need JTAG? it just needs some way to get data back and forth.
<whitequark> https://github.com/m-labs/microscope works over UART, for example
<whitequark> of course you could do it over JTAG. you could also not.
<hackerfoo> I think it's described in "Tandem Configuration" (p155) in https://www.xilinx.com/support/documentation/ip_documentation/pcie_7x/v3_3/pg054-7series-pcie.pdf
<promach> whitequark: what if you need to debug the PCIe design coding itself ?
<hackerfoo> You need Vivado 2018.3 or later, and partial reconfiguration is now available in 2019.1 WebPack for free.
<promach> will UART as ILA channel be feasible at all ?
<hackerfoo> promach (IRC): Do that with the case open, then once you have that figured out, you don't need the external debugger.
<whitequark> ^
<promach> hackerfoo: no, UART is way slower than PCIe
<whitequark> JTAG is also way slower than PCIe.
<hackerfoo> You have a huge amount of bandwidth once PCIe is up.
<whitequark> I debug my PCIe PHY over an UART, actually
<whitequark> I don't need to sample every symbol on wire continuously, I don't even have any way to analyze that
<whitequark> instead I fill a buffer and read it out later.
<whitequark> or compute statistics
<promach> that buffer is going to be very big if you use UART instead of JTAG
<whitequark> i don't see why
<mwk> PCIe is so much faster than both that it doesn't really matter
<whitequark> ^
<mwk> what you need is good triggers to get the data you want
<whitequark> i'm essentially never interested in raw data. what i'm interested in is things like "what were the last 10 different states of LTSSM"?
<whitequark> or "what was the last TS1 i got"
<whitequark> that's not even a kilobyte
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<promach> ok
<mwk> also: PCIe is ~100 times faster than JTAG; this means that, given a buffer of a const size, JTAG will drain about 1% of it in the time it takes for PCIe to fill it completely
<whitequark> if i do sample raw data then often a kilobyte of symbols is enough to determine things like
<whitequark> "the SERDES didn't align to a comma"
<mwk> having 1% of extra buffer capacity compared to UART means basically nothing
<whitequark> ^
<freeemint> promach, hackerfoo thanks for your input. I was not aware of croud supply
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<freeemint> https://www.crowdsupply.com/sutajio-kosagi/fomu sounds fun too. but it's price/performance is anything but stellar.
<hackerfoo> There's also the PicoEVB by the same guy as the NiteFury with a 35T, 1xPCie, and built in JTAG: https://picoevb.com
<hackerfoo> The reason for no built-in JTAG on the NiteFury is that you can't have both USB and 4xPCIe over M.2: https://en.wikipedia.org/wiki/M.2#Form_factors_and_keying
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<pepijndevos> whitequark, re generics initialisation with nmigen/vhdl/whatever: https://github.com/tgingold/ghdlsynth-beta/issues/46
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<zignig> hackerfoo: popr is nifty, I think it should be _up_ and _down_ with time _left_ to _right_.
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<hackerfoo> zignig: huh? I don't understand what you're suggesting.
<Ultrasauce> is this isr orthogonality
<Ultrasauce> er isa
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<hackerfoo> zignig: Ah, I see your GitHub issue. Popr syntactically looks a little like Forth, but it uses lazy graph reduction at compile time to schedule operations, hence the weird grabbing diagram in the tutorial.
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<hackerfoo> So it's more like Haskell, where data is "pulled" rather than "pushed."
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<zignig> hackerfoo: understood , I like that it won't evaluate anthing that is not outside , it is _actually_ linear but can be evaluated consurrent if you can.
* zignig has been doing PLC ladder logic for the last few months , I grok.
<gruetzkopf> all i ever do on PLCs is i-cant-believe-it's-not-pascal (ST)
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<zignig> gruetzkopf: been doing MW solar farms , so cool !
<gruetzkopf> oh, cool
<zignig> in .au
<gruetzkopf> this is automation around my lab signalbox (rail safety)
<gruetzkopf> (Which implements all it's logic in relays)
<zignig> still I like the low level logic , you have to sehlah (pause and consider) before every change.
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<gruetzkopf> the fun thing about the signalbox interlocking logic is that it's basically a object-oriented system, with exactly three different interfaces. you have one box full of relays (always the same) for each point, one for each signal etc and just plug them together the way your tracks are connected together
<gruetzkopf> and then it'll do shortest path search based on relay delays..
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<azonenberg> zignig: eeeew ladder logic
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<GenTooMan> relay logic haven't looked at that in a while. IEC 61131-3 type stuff?
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<tnt> u
<tnt> Is verilator faster than iverilog ? I've been using the latter mostly, but some sim take a long time ...
<daveshah> Verilator is faster to run but has longer build times (because it compiles to a binary)
<daveshah> Beware that it doesn't implement the usual simulation semantics, so you'll have to have a testbench in C++
<tnt> Yeah, that's the annoying part and why I haven't used it yet :/
<tnt> Aslo do you know if it scales to multi-core well ?
<tnt> Here I'm getting in the 20-30 min sim time so it's worth considering alternatives :p
<daveshah> In theory it has some multithreading, I'm not sure how much actual benefit that brings
<azonenberg> tnt: 20-30 minute sim times? not 20-30 days? oh, i wish i had your problems
<tnt> azonenberg: Hehe, yeah, this is just the beginning :p I never quite got to 20-30 days, but I sure did quite a few overnight kind of sim back when I was working on Digital Cinema stuff.
<tnt> (but that was modelsim, not iverilog)
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<Finde> verilator can be easily 10-100x faster than iverilog
<Finde> from my experience
<Finde> I think the dimensionless bar charts from the verilator 4.0 talk claimed something like a 5x improvement over the fastest commercial simulator when running on O(10) cores
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