<sorear> Does typ mean anything?
<sorear> yes, I know what it stands for
<whitequark> "what we wish our parts would work like"
emeb_mac has quit [Ping timeout: 245 seconds]
emeb_mac has joined ##openfpga
rohitksingh has joined ##openfpga
Richard_Simmons has joined ##openfpga
rohitksingh has quit [Ping timeout: 276 seconds]
<azonenberg> sorear: some arbitrary average value that most parts are kinda close to, but you can't rely on it
<azonenberg> :p
Richard_Simmons has quit [Ping timeout: 276 seconds]
rohitksingh has joined ##openfpga
Bob_Dole has quit [Ping timeout: 276 seconds]
<cyrozap> gruetzkopf: I just noticed you were doing stuff with the Pano Logic G2--I did some RE work on that in the past, so if you have any questions feel free to ask.
<cyrozap> If you're also working with misoc/migen, you may also find these repos/branches interesting: https://github.com/cyrozap/migen/tree/pano-g2-support https://github.com/cyrozap/misoc/tree/uart-over-jtag
Jybz has joined ##openfpga
Bob_Dole has joined ##openfpga
Bob_Dole has quit [Ping timeout: 276 seconds]
emeb_mac has quit [Ping timeout: 244 seconds]
rohitksingh has quit [Ping timeout: 276 seconds]
rohitksingh has joined ##openfpga
<gruetzkopf> i'm stealing your DVI encoder blocks, most other stuff (including DDR2) i already have
Asu has joined ##openfpga
rohitksingh has quit [Remote host closed the connection]
zino has quit [Ping timeout: 245 seconds]
zino has joined ##openfpga
<pepijndevos> A physical explanation of setup and hold times :)) https://www.youtube.com/watch?v=joqxfIbH2eE
<Sprite_tm> pepijndevos: Hehe, that was more or less what I was thinking :P pipelining marbles, yeah :)
lutsabound has joined ##openfpga
sunxi_fan has joined ##openfpga
sunxi_fan has quit [Quit: Leaving.]
sunxi_fan has joined ##openfpga
sunxi_fan has quit [Client Quit]
zng has joined ##openfpga
indy has quit [Ping timeout: 268 seconds]
indy_ has joined ##openfpga
indy_ has quit [Quit: ZNC - http://znc.sourceforge.net]
indy has joined ##openfpga
pinoaffe has joined ##openfpga
rohitksingh has joined ##openfpga
lutsabound has quit [Quit: Connection closed for inactivity]
kc8apf has quit [Ping timeout: 252 seconds]
kc8apf has joined ##openfpga
eddyb has quit [Ping timeout: 250 seconds]
eddyb has joined ##openfpga
lutsabound has joined ##openfpga
zkms has quit [Quit: zkms]
zkms has joined ##openfpga
emeb_mac has joined ##openfpga
<eddyb> this has far more cool diagrams than I expected given the paywall abstract. also, RISC-V?! https://sci-hub.tw/downloads/2019-08-28/73/10.1038@s41586-019-1493-8.pdf
<eddyb> I should just install some kind of extension that opens up paywalls in case I might miss something cool
<eddyb> bonus points if it's called "denature"
emeb has joined ##openfpga
Asu has quit [Ping timeout: 244 seconds]
Asu` has joined ##openfpga
<sorear> assuming that’s the CNFET paper, it’s not conformant and would violate the trademark if sold, they made up an incompatible 16 bit version …
lutsabound has quit [Quit: Connection closed for inactivity]
lutsabound has joined ##openfpga
<tpw_rules> sorear: my understanding was that it had a 16 bit ALU and datapath but was still legal
<tpw_rules> oh, maybe i misread the abstract
<tpw_rules> "runs standard 32-bit instructions on 16-bit data and addresses" could be both ways
<tpw_rules> well that's sad
<tpw_rules> why would they do that
emeb has quit [Quit: Leaving.]
cr1901_modern has quit [Ping timeout: 245 seconds]
Asu` has left ##openfpga ["Konversation terminated!"]
Jybz has quit [Ping timeout: 252 seconds]
Hoernchen has quit [Ping timeout: 246 seconds]
marcan has quit [Ping timeout: 264 seconds]
marcan has joined ##openfpga
Hoernchen has joined ##openfpga
stefanct has quit [Changing host]
stefanct has joined ##openfpga
Hoernchen has quit [Read error: Connection reset by peer]
Hoernchen has joined ##openfpga
moho1 has quit [Quit: WeeChat 2.2]
cr1901_modern has joined ##openfpga