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<GenTooMan>
hopefully that will be enough for me to put some of it together. I'll try to see if I can differentiate between synthesis and simulation like in verilog now.
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<bubble_buster>
Is there any existing implementation of RISC V debug spec? Or is the spec still changing too much?
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<Finde>
bubble_buster: I thought that PULP were using a spec-compliant controller as of some recent version
<bubble_buster>
Finde: thanks I will check that out
<sorear>
rocket is also spec compliant for a while, including all of the hifive boards iirc
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<emily>
sorear: I heard the first hifive board had unusable debug protocol or something?
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<kc8apf>
Talking with u-bmc folks, they got the impression Aspeed u-boot wasn't going to be upstreamed. Instead, they hacked up their own init code and skipped u-boot entirely
<kc8apf>
They are also talking about load/verify/decompress times which I know has been a topic here as well
<kc8apf>
Hopefully there can be some cooperation
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<kc8apf>
*sigh* too many channels that start with open
<GenTooMan>
It's kind of frustrating everyone wants to start open ... :D
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<ZirconiumX>
I mean, I think this channel name is something of an artefact from when there actually was an "openfpga"
<swedishhat[m]>
That's pretty cool, ZirconiumX . Do you mean open on like the silicon level?
<ZirconiumX>
No, as in the program by azonenberg
<sorear>
it… still exists. Link in topic
<azonenberg>
well the original plan was for that github repo to be the community's development platform for all sorts of open source fpga tools
<azonenberg>
it ended up just having greenpak stuff and a little coolrunner code
<azonenberg>
because symbiflow etc is all separate
<ZirconiumX>
azonenberg: Didn't the greenpak chips come pretty close to being open platforms, though?
<ZirconiumX>
Or am I just imagining things?
<sorear>
silego published docs for gp4 and gp5
<sorear>
as a reward, they’ve gotten a complete lack of interest in gp5
<sorear>
imo this is a problem for us politically
<sorear>
if we want to convince a new vendor to release docs, we need to convince them they will get more in return than gp5
<azonenberg>
Well most of that was just me not having time to work on it
<azonenberg>
Nobody else was doing development
<azonenberg>
And my house project hit right then
<azonenberg>
(side note, they published docs before i started the project, not be cause of me)
<azonenberg>
I started my toolchain pre symboflow, pre prjxray
<azonenberg>
i dont even think the ice40 stuff was public yet
<azonenberg>
this channel had like ten people in it
<ZirconiumX>
In other news, I'm semi-confident in my Bresenham implementation
<ZirconiumX>
It passes cardinal and diagonal direction tests at least.
<sorear>
that makes it a bit better then, I thought it was because of you
<azonenberg>
sorear: in fact, it was the opposite
<azonenberg>
I chose greenpak as the target device *because* it required no RE
<azonenberg>
and the bitstream was already public
<mwk>
ZirconiumX: wanna share?
<ZirconiumX>
GreenPAKs are tiny though, right?
<azonenberg>
ZirconiumX: yes, 26 LUTs for the device i was initially targeting
<azonenberg>
They're meant for power rail/reset sequencing and other simple stuff
<azonenberg>
not to run a softcore CPU :p
<azonenberg>
That said, i've managed to cram a lot of stuff into them
<ZirconiumX>
mwk: I just got in bed, but I can show you some slightly older code with a few fixed bugs
<azonenberg>
like a minimal UART iirc, or even autonegotiation for 10baseT