:( I think my icebreaker might be kill
is there some jumper or something required to program icebreaker?
when I plug it in via usb it either dimly lights up or does a lot of blinking
but does not show up in lsusb
with same cable and usb port, upduino does show up in lsusb
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I think I created a short when I soldered the pmod headers
one of the voltage regulators gets extremely hot as soon as I plug it in
my soldering is definitely sloppy but I don't see any shorts
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I'll try desoldering tomorrow. guess I should order a multimeter or something to check for shorts in the future
got my upduino to work at least
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which regulator ?
The one further from the usb port
Closer to flash
Did you solder anything to the 'RGB' header ?
No just the pair of pmod headers
That's the 1v2 regulator, and that power rails isn't exposed to PMODs, so that's weird.
anyone know the proper way to shout documentation corrections at Lattice, or should I just be shouting them into the void? ^^
[I figure if someone's gone through the effort of figuring that out, it's likely someone in here =P]
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hi guys, me again... so looking at the datasheet for the ECP5 it says that for LVDS pairs you can omit the (-) pin of the pair in the design and only specify the IO_TYPE to LVDS for both ends of the pair, does this also apply for the yosys/trellis/nextpnr?
whitequark, thanks allot! I was kind of confused because in xilinx land for example you use IBUFDS and explicitly hook both ends of the pair.
Not sure about the ECP5 but for the ice40 it's not even that you _can_ .. you have to :) There is no way to do it with both wires and having anything connector / assigned to the other wire in the pair will actually cause a conflict and not build.
on ECP5 you could use one of their primitives that hooks up both P and N pins
ah no I think you have to do that on ECP5 too
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ktemkin: You can DM me the bug in the documentation. I would forward it to the product manager of ECP5. In the past I forwarded bugs in the ice40 documentation found by whitequark to the product manager of ice40. I dont know if or when a new documentation gets released with the fixes. Sending in bug reports buys us some good will.
whitequark, tnt, yes, as far as I understand non of the IOB primitives have pairs for LVDS so its implicitly inferred, looking at the examples from FleaFPGAOhm indeed it's using only the positive end of the pair