<hackerfoo> emily: #clash-lang
<hackerfoo> Is a single mux better than a daisy chain? Or maybe the same thing will be inferred anyway.
<sorear> dunno about fpga tools but in asic land it’s expected that daisy chains will be optimized into priority encoders
<sorear> maybe I shouldn’t speak so generally, I’ve only talked to one person about this specifically
<hackerfoo> sorear: A priority encoder controlling a mux? Like if you use `assign out = cond_a ? a : cond_b ? b : ...;` ?
<hackerfoo> For context, most data is passed through in a functional way, but for linear things like arrays, it seems like it would be bad to string address, data in & data out lines through the functional chain.
<sorear> yes, this came up in a context with 32 muxes in sequence
<hackerfoo> So, instead, array access is through a bus, where those lines will have to be muxed to some shared block of RAM.
<hackerfoo> At first I though of a tristate bus with a token passed to control access, but it seems that you can't have that sort of bus in an FPGA.
<hackerfoo> It seems like that would be the way to do it in an ASIC.
<sorear> everything I’ve seen in recent (mostly academic) designs uses muxes, would be interesting to know if the higher-resourced players are doing tristates
<sorear> anything that’s not synthesizable seems slowly on the way out
<sorear> 8-bit-era cpus had internal tristate buses, but they weren’t synthesized
<Sprite_tm> I think Xilinx had tristate buses in fpgas a long time ago. Must've been fun, allows you to model a short circuit in Verilog.
<sorear> they did, it’s come up here before
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<hackerfoo> I found this article explaining it when looking to see if a tristate bus is possible: http://fpgasite.blogspot.com/2017/05/fpga-internal-tri-state-buses.html
<hackerfoo> (on an FPGA)
<hackerfoo> But I guessed that it wasn't given previous experience with `wor` and `wand` in Vivado.
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<hackerfoo> I guess ISE supported them, and Vivado does with a flag, so they purposefully removed them.
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<GenTooMan> I'm not sure having a tristate bus internally is useful myself however it's not like I have spent more than a few weeks time messing with them.
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<hackerfoo> Ah, I can still `or` the wires together, and that seems like it would be faster than muxing. Easier, at least.
<whitequark> yes, it's actually faster
<whitequark> misoc used that for its internal CSR bus
<whitequark> instead of external address decoders and muxes on wishbone, csr bus used internal (inside the peripheral) address decoders and oring instead of muxes
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<hackerfoo> whitequark: Thanks.
<hackerfoo> This is a lot easier since each thing on the bus is already sequenced, so no need for request & ack lines, priority logic, and a big mux.
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<freemint> Any opinions on EFINIX (an FPGA startup)?
<tpw_rules> ooh it has quantum gates
<tpw_rules> although it does appear you can actually buy them
<freemint> Yeah they even have a cheapish board on crowd supply
<TD-Linux> someone is working on yosys (but not nextpnr) support
<tpw_rules> are they being forthcoming with bitstream formats?
<freemint> their quantum gate technology boils down to "Our cells can be used as router and as LUT" i think
<TD-Linux> I am not sure why you would use this over an ice40
<tpw_rules> router? like they have more muxes than average?
<freemint> router -> routing matrix (the interconnect)
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<freemint> TD-Linux, I am not sure either but more companies at the low end are not bad for consumer.
<tpw_rules> freemint: oh i thought that was integrated into the cells already. i guess not
<freemint> Also they aim for higher performance once in the long run. A triopoly might be preferable to a duopoly. As for technical reasons: I have no idea of FPGA technology
<freemint> I am only going by their advertisment material do not quote me on it: https://www.efinixinc.com/technology.html
<TD-Linux> freemint, sortof. I mean we're in ##openfgpa, I would not use it without nextpnr support.
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<freemint> The toolchain is not open sourced
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<freemint> There was some past discussion of this: https://freenode.irclog.whitequark.org/~h~openfpga/2019-06-28
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