<kc8apf>
sensille: in that new FPGA manufacturers popping up is pretty rare
<kc8apf>
Looking though the execs involved, it's a mix of ex-Altera, Xilinx, Silicon Blue, etc
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<tnt>
Not much doc available publically, that doesn't really motivate me to use their stuff ..
<kc8apf>
Their headquarters is 10 minutes from my house
<tnt>
So you're ... proposing a heist of their doc ?
<whitequark>
дщд
<whitequark>
*lol
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<q3k>
лол
<whitequark>
so i figured out what kind of design i want for all remaining boneless instructions
<whitequark>
"jump through switch table" just needs to be a slightly different kind of multicycle
<whitequark>
it's like one flop and it allows me to not add another huge adder
<whitequark>
really, the moment you stop going for RISC purity, all the problems just solve themselves
<whitequark>
boneless now has 4 16-bit adders i think? PC+1, PC+1+imm, Ra+(PC+1+imm|imm) and the one in ALU
<whitequark>
and they can all run in parallel with memory accesses
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<whitequark>
daveshah: out of curiosity, how many logic levels on ice40 would 16 layers of carries be equivalent to?
<whitequark>
sounds like somethig you'd know offhan
<daveshah>
probably about 3 or 4
<daveshah>
maybe fewer depending on routing delays (which softlogic has but carries don't)
<whitequark>
hm, so i should very heavily optimize decode logic
<sorear>
does lut cascade change that then
<daveshah>
In theory, in practice it usually just adds routing delay elsewhere because it causes a less optimal placement
<daveshah>
In some cases it could probably be used opportunistically for some small improvements, but in practice I've found that hard to see
<sorear>
there's so much suboptimality in the synthesis -> packing -> placement -> routing phase-ordering problem :(
<daveshah>
In new nextpnr arches I think we will avoid packing as much as possible, as the packing->placement step is particularly annoying
<daveshah>
With the analytical placer far fewer validity checks are needed so placing finer grained cells is much more feasible]
<whitequark>
can this be done for ice40 too?
<daveshah>
Maybe, but it doesn't seem like there would be that much point
<daveshah>
e.g. you have to use the LUT to get to the register
<daveshah>
nor do the register and LUT have separate outputs
<cr1901>
>boneless now has 4 16-bit adders i think? PC+1, PC+1+imm, Ra+(PC+1+imm|imm) and the one in ALU
<cr1901>
How much extra resources is this compared to the previous version?
<daveshah>
In any case, for iCE40 we already place logic cells rather than whole tiles, so it's much less packing than most traditional flows
<whitequark>
cr1901: v3 should be much more compact than v2 in general
<whitequark>
the target is 300 LUT without compromising on ISA orthogonality
<sorear>
daveshah: what's a "whole tile" in this context?
<whitequark>
i'm not sure if you could fit it into iCE40LP384, and it doesn't have any RAM anyway
<daveshah>
sorear: 8 logic cells
<cr1901>
That's good. I have a potentially horrible experiment I want to do w/ boneless on machxo2 once I've done more REing and I hook it into the nextpnr python API for generic arch
<cr1901>
s/potentially//
<whitequark>
an LP640 looks like a better fit, except ... the lattice doc is contradicting itself
<sorear>
it is highly surprising to me if the following are all true: (a) Diamond does pre-placement packing of 8 LUTs into tiles (b) nextpnr does not (c) Diamond's QOR is generally better than nextpnr
<whitequark>
it says max 25 programmable IO but the largest package it has is WLCSP16
<daveshah>
sorear: no Diamond doesn't
<cr1901>
machxo2 specifically b/c it has distributed RAM and an internal ROM for user code
<daveshah>
I was referring to traditional flows in the sense of traditional academic flows (e.g. VPR)
<daveshah>
(nor does icecube afaik)
<sorear>
huh
<whitequark>
cr1901: boneless is specifically written to not touch distributed RAM
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<cr1901>
I can turn dist RAM into block RAM
<sorear>
is that something everybody independently fixed after adopting?
<daveshah>
Yes, pretty sure they have various ways of permuting the packing, etc
<cr1901>
it's a contingency. The user internal ROM is more imporatnt
<cr1901>
which means no need for a damn slow SPI flash connection if I can fit everything into 8k of user ROM and 4k of RAM
<whitequark>
oh sure
<cr1901>
which... idk, we'll see.
<whitequark>
which chip is that?
<daveshah>
whitequark: LP640 is just a 1k afaik
<whitequark>
4kbyte or kbit??
<daveshah>
(assuming this is referring to ice40 and not xo2)
<whitequark>
daveshah: yeah, ice40
<whitequark>
LP384 would b a cute demo
<daveshah>
The limit of 384 total state bits is a bit tricky
<whitequark>
boneless has very few state bits
<whitequark>
about 68 plus the FSM state
<whitequark>
plus for LP384 the bus multiplexer state
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<kc8apf>
tnt: I'm not opposed to sitting in their lobby until they release docs
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