dj_pi has quit [Ping timeout: 272 seconds]
emeb has quit [Quit: Leaving.]
gsi_ has joined ##openfpga
gsi__ has quit [Ping timeout: 258 seconds]
dj_pi has joined ##openfpga
dj_pi has quit [Ping timeout: 245 seconds]
dj_pi has joined ##openfpga
dj_pi has quit [Read error: Connection reset by peer]
Bike has quit [Quit: Lost terminal]
sgcarnaval has quit [Remote host closed the connection]
m_w has joined ##openfpga
Thorn has quit [Ping timeout: 272 seconds]
qualia has quit [Quit: well, bye,]
tpw_rules has quit [Quit: byeeee]
tpw_rules has joined ##openfpga
rohitksingh_work has joined ##openfpga
Jybz has joined ##openfpga
<kc8apf> Efinix Trion T8 FPGA
<sorear> hmm, they're very new
<sorear> first funding round 2017, "volume production" "march 29, 2019"
<sorear> https://www.efinixinc.com/products-efinity.html says they have a contract with verific
<kc8apf> it'll be interesting to see where they end up with pricing
indy has quit [Ping timeout: 246 seconds]
Miyu has joined ##openfpga
vonnieda_ has joined ##openfpga
vonnieda has quit [Ping timeout: 276 seconds]
swedishhat[m] has quit [Read error: Connection reset by peer]
nrossi has quit [Read error: Connection reset by peer]
henriknj has quit [Write error: Connection reset by peer]
kervel has quit [Remote host closed the connection]
jfng has quit [Read error: Connection reset by peer]
xobs has quit [Remote host closed the connection]
indefini[m] has quit [Write error: Connection reset by peer]
thehurley3[m] has quit [Remote host closed the connection]
nrossi has joined ##openfpga
emeb_mac has quit [Ping timeout: 245 seconds]
Bob_Dole has quit [Read error: Connection reset by peer]
Bob_Dole has joined ##openfpga
Jybz has quit [Remote host closed the connection]
indefini[m] has joined ##openfpga
xobs has joined ##openfpga
henriknj has joined ##openfpga
thehurley3[m] has joined ##openfpga
jfng has joined ##openfpga
swedishhat[m] has joined ##openfpga
kervel has joined ##openfpga
Jybz has joined ##openfpga
Asu has joined ##openfpga
OmniMancer has joined ##openfpga
Thorn has joined ##openfpga
vonnieda has joined ##openfpga
AndrevS has joined ##openfpga
Jybz has quit [Remote host closed the connection]
vonnieda_ has quit [Ping timeout: 276 seconds]
keesj_ has quit [Ping timeout: 246 seconds]
keesj has joined ##openfpga
s_frit has quit [Remote host closed the connection]
s_frit has joined ##openfpga
_whitelogger has joined ##openfpga
finsternis has quit [Excess Flood]
finsternis has joined ##openfpga
<_whitenotifier-3> [whitequark/Boneless-CPU] whitequark pushed 1 commit to master [+6/-5/±6] https://git.io/fjoR7
<_whitenotifier-3> [whitequark/Boneless-CPU] whitequark 6412823 - Hopefully finalize {LD,ST}{,R,X,XA}, MOV{R,I}, JAL.
keesj has quit [Ping timeout: 244 seconds]
keesj has joined ##openfpga
<q3k> kc8apf: do they say anywhere what an 'LE' is
pie_ has quit [Ping timeout: 250 seconds]
Thorn has quit [Ping timeout: 245 seconds]
<edmund_> kc8apf: I do have two development boards with Trio T20 FPGAs here in my hands.
<edmund_> I guess T4, T8, T13, and T20 are all the same die. Everthing else would not make sense.
<q3k> sorear: oh cool
<q3k> so it's very close to a ice40
<sorear> https://www.efinixinc.com/docs/an006-configuring-trion-fpgas-v2.0.pdf#page=3 was not expecting to see "call for quote" here
<q3k> yeah these might not exist yet
<sorear> who decided fpga multipliers should always be multiples of 9 bits
<ironsteel> exactly.... but I can't come up with a reason for that, someone here may know...
<ironsteel> which brings me to M9K memory blocks in altera land, thay are 9K because of parity - 8,192 bits + 1024 bits for parity
<sorear> for some reason I thought altera did 5-10-20-40 memories (ECC to 32)
<sensille> ecc with 2 bits per 8?
<sorear> more like 8 per 32, extended Hamming code
<sensille> are those trion interesting?
rohitksingh has joined ##openfpga
Thorn has joined ##openfpga
ironsteel has quit [Quit: Ex-Chat]
Hamilton has joined ##openfpga
noobineer has quit [Ping timeout: 276 seconds]
Hamilton2 has joined ##openfpga
Hamilton2 has quit [Remote host closed the connection]
Hamilton2 has joined ##openfpga
Hamilton has quit [Ping timeout: 268 seconds]
noobineer has joined ##openfpga
somlo has quit [Quit: Leaving]
rohitksingh has quit [Ping timeout: 245 seconds]
somlo has joined ##openfpga
rohitksingh_work has quit [Read error: Connection reset by peer]
vonnieda has quit [Quit: My MacBook Pro has gone to sleep. ZZZzzz…]
lopsided98_ has quit [Remote host closed the connection]
<_whitenotifier-3> [whitequark/Boneless-CPU] whitequark pushed 1 commit to master [+0/-0/±1] https://git.io/fjozP
<_whitenotifier-3> [whitequark/Boneless-CPU] whitequark 2bcd391 - Update design.
lopsided98 has joined ##openfpga
vonnieda has joined ##openfpga
genii has joined ##openfpga
<kc8apf> sensille: in that new FPGA manufacturers popping up is pretty rare
<kc8apf> Looking though the execs involved, it's a mix of ex-Altera, Xilinx, Silicon Blue, etc
pie_ has joined ##openfpga
<tnt> Not much doc available publically, that doesn't really motivate me to use their stuff ..
<kc8apf> Their headquarters is 10 minutes from my house
<tnt> So you're ... proposing a heist of their doc ?
<whitequark> дщд
<whitequark> *lol
emeb has joined ##openfpga
GenTooMan has quit [Quit: Leaving]
Hamilton2 has quit [Quit: Leaving]
Hamilton has joined ##openfpga
rohitksingh has joined ##openfpga
finsternis has quit [Excess Flood]
finsternis has joined ##openfpga
GenTooMan has joined ##openfpga
<q3k> лол
<whitequark> so i figured out what kind of design i want for all remaining boneless instructions
<whitequark> "jump through switch table" just needs to be a slightly different kind of multicycle
<whitequark> it's like one flop and it allows me to not add another huge adder
<whitequark> really, the moment you stop going for RISC purity, all the problems just solve themselves
<whitequark> boneless now has 4 16-bit adders i think? PC+1, PC+1+imm, Ra+(PC+1+imm|imm) and the one in ALU
<whitequark> and they can all run in parallel with memory accesses
GenTooMan has quit [Quit: Leaving]
GenTooMan has joined ##openfpga
<whitequark> daveshah: out of curiosity, how many logic levels on ice40 would 16 layers of carries be equivalent to?
<whitequark> sounds like somethig you'd know offhan
<daveshah> probably about 3 or 4
<daveshah> maybe fewer depending on routing delays (which softlogic has but carries don't)
<whitequark> hm, so i should very heavily optimize decode logic
<sorear> does lut cascade change that then
<daveshah> In theory, in practice it usually just adds routing delay elsewhere because it causes a less optimal placement
<daveshah> In some cases it could probably be used opportunistically for some small improvements, but in practice I've found that hard to see
<sorear> there's so much suboptimality in the synthesis -> packing -> placement -> routing phase-ordering problem :(
<daveshah> In new nextpnr arches I think we will avoid packing as much as possible, as the packing->placement step is particularly annoying
<daveshah> With the analytical placer far fewer validity checks are needed so placing finer grained cells is much more feasible]
<whitequark> can this be done for ice40 too?
<daveshah> Maybe, but it doesn't seem like there would be that much point
<daveshah> e.g. you have to use the LUT to get to the register
<daveshah> nor do the register and LUT have separate outputs
<cr1901> >boneless now has 4 16-bit adders i think? PC+1, PC+1+imm, Ra+(PC+1+imm|imm) and the one in ALU
<cr1901> How much extra resources is this compared to the previous version?
<daveshah> In any case, for iCE40 we already place logic cells rather than whole tiles, so it's much less packing than most traditional flows
<whitequark> cr1901: v3 should be much more compact than v2 in general
<whitequark> the target is 300 LUT without compromising on ISA orthogonality
<sorear> daveshah: what's a "whole tile" in this context?
<whitequark> i'm not sure if you could fit it into iCE40LP384, and it doesn't have any RAM anyway
<daveshah> sorear: 8 logic cells
<cr1901> That's good. I have a potentially horrible experiment I want to do w/ boneless on machxo2 once I've done more REing and I hook it into the nextpnr python API for generic arch
<cr1901> s/potentially//
<whitequark> an LP640 looks like a better fit, except ... the lattice doc is contradicting itself
<sorear> it is highly surprising to me if the following are all true: (a) Diamond does pre-placement packing of 8 LUTs into tiles (b) nextpnr does not (c) Diamond's QOR is generally better than nextpnr
<whitequark> it says max 25 programmable IO but the largest package it has is WLCSP16
<daveshah> sorear: no Diamond doesn't
<cr1901> machxo2 specifically b/c it has distributed RAM and an internal ROM for user code
<daveshah> I was referring to traditional flows in the sense of traditional academic flows (e.g. VPR)
<daveshah> (nor does icecube afaik)
<sorear> huh
<whitequark> cr1901: boneless is specifically written to not touch distributed RAM
Hamilton has quit [Quit: Leaving]
<cr1901> I can turn dist RAM into block RAM
<sorear> is that something everybody independently fixed after adopting?
<daveshah> Yes, pretty sure they have various ways of permuting the packing, etc
<cr1901> it's a contingency. The user internal ROM is more imporatnt
<cr1901> which means no need for a damn slow SPI flash connection if I can fit everything into 8k of user ROM and 4k of RAM
<whitequark> oh sure
<cr1901> which... idk, we'll see.
<whitequark> which chip is that?
<daveshah> whitequark: LP640 is just a 1k afaik
<whitequark> 4kbyte or kbit??
<daveshah> (assuming this is referring to ice40 and not xo2)
<whitequark> daveshah: yeah, ice40
<whitequark> LP384 would b a cute demo
<daveshah> The limit of 384 total state bits is a bit tricky
<whitequark> boneless has very few state bits
<whitequark> about 68 plus the FSM state
<whitequark> plus for LP384 the bus multiplexer state
AndrevS has quit [Remote host closed the connection]
_whitelogger has joined ##openfpga
somlo has quit [Quit: Leaving]
somlo has joined ##openfpga
rohitksingh has quit [Ping timeout: 244 seconds]
davidc__ has joined ##openfpga
OmniMancer has quit [Quit: Leaving.]
<kc8apf> tnt: I'm not opposed to sitting in their lobby until they release docs
Miyu has quit [Ping timeout: 252 seconds]
zng has quit [Ping timeout: 246 seconds]
yhetti has quit [Ping timeout: 244 seconds]
mossmann has quit [Ping timeout: 272 seconds]
zng has joined ##openfpga
yhetti has joined ##openfpga
mossmann has joined ##openfpga
vonnieda has quit [Quit: My MacBook Pro has gone to sleep. ZZZzzz…]
vonnieda has joined ##openfpga
Asu` has joined ##openfpga
Asu has quit [Ping timeout: 246 seconds]
lutsabound has joined ##openfpga
Bike has joined ##openfpga
Morn_ has quit [Ping timeout: 252 seconds]
Morn_ has joined ##openfpga
vonnieda has quit [Quit: My MacBook Pro has gone to sleep. ZZZzzz…]
Asu has joined ##openfpga
Asu` has quit [Ping timeout: 248 seconds]
Asu has quit [Remote host closed the connection]
genii has quit [Remote host closed the connection]