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<pointfree>
"...Access to this documentation on the infineon website is only granted after accepting a NDA like license. This license forbids publishing any information from these documents, except where one can prove that this information was previously published."
<pointfree>
Infineon's aquisition of Cypress does not bode well for PSoC
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<hl>
oh god they acquired cypress? fuck
<hl>
better start archiving datasheets
<cr1901_modern>
YIKES
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<hl>
i really feel that there should be a 'wikileaks for datasheets', but I guess people ideologically pissed off about this stuff and who actually have access to them is not a large domain ;)
<pointfree>
libgen/scihub should do datasheets too
<pointfree>
I'm going to suck down all of cypress.com with wget tomorrow. Someone with a cypress forum account could be of help (more access to the website). I'll likely put up a tarball, torrent, or download listing on psoctools.org later.
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<hl>
i don't think libgen prohibits datasheets as such but it's definitely not its focus/intent
<hl>
and then there's paywalled standards, which we don't really have a scihub for
<hl>
(although, scihub does work for IEEE standards if you point it at ieeexplore.ieee.org)
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<mwk>
hey, suppose you're making a configurable output buffer for a silicon chip
<mwk>
with configurable slew rate
<mwk>
how would you implement that in hardware? three different output transistors with some kind of differing physical characteristics?
* mwk
looking at configuration bits for a certain FPGA and trying to make heads or tails of them
<sorear>
that sounds like a detail that’s probably in a patent
<tnt>
Ah well, same idea, delaying the rise of the output transistor gate voltage :) I guess adding a series resistor is easier. But same principle, you have a RC created by the pre-driver output impedance and output driver gate capacitance.
<mwk>
hm... so if I disable all slew rate bits, I end up with no voltage on that thing and output doesn't work at all
<mwk>
that's an easy enough theory to test
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<sorear>
azonenberg_work: implementing register files for dual-issue RISC on FPGAs has just come up in #yosys
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