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<bsilvereagle> Anyone know if mtvre is happening this month?
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<digshadow> bsilvereagle: mtvre details are almost resolved, time window needs to be confirmed: https://www.meetup.com/Mountain-View-Reverse-Engineering-Meetup/events/262089016/
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<ZirconiumX> This might not be the right channel for this, but tnt pointed me here, so
<ZirconiumX> As a test, I tried to reimplement a 74x153 dual 4:1 mux in Verilog
<daveshah> Not sure if Icarus supports assert, see https://github.com/steveicarus/iverilog/issues/193
<ZirconiumX> Verilator accepts this code, as does Yosys, but Icarus says I have malformed statements without any more information
<ZirconiumX> Oh, excellent.
<ZirconiumX> So what should I use to simulate my program? Yosys seems to do okay, although I can't actually tell if my code is running properly
<ZirconiumX> (and yes, I'm looking at the VCD)
<whitequark> use preprocessor to eliminate asserts, i guess
<daveshah> Yosys is definitely not the right tool here, it doesn't implement any kind of traditional event model and will be discarding the delays
<daveshah> as is standard for synthesis tools
<daveshah> The `sim` command is really for simulating an elaborated/synthesised circuit rather than traditional simulation
<ZirconiumX> Well, verilator seems to have issues with $dumpfile/$dumpvars
<ZirconiumX> And Icarus doesn't do asserts
<daveshah> Verilator doesn't implement the event model or delays either
<daveshah> I think you have to use the C/C++ API which you'd use for stimuli etc to enable VCD tracing too
<daveshah> If you want to use Icarus there are various fake assert options like https://stackoverflow.com/a/31302223
<ZirconiumX> Thank you, daveshah
<ZirconiumX> Also, should I be worried about a Verilator UNOPTFLAT warning?
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