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<rombik_su> whitequark: Hi! Sorry to bother you, but can you check my twitter DM at your earliest convenience?
<whitequark> rombik_su: yes, i've seen your DM
<rombik_su> whitequark: oh, ok.
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<mithro> Has anyone played with https://github.com/emsec/hal ?
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<tnt> Does icestorm have a tool to generate a verilog 'structural' netlist (i.e. instances of LUT / Register / ...) from a .asc ?
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<mithro> tnt: I believe so?
<tnt> mithro: I didn't find it :/
<tnt> I was trying to get a verilog I could feed to https://github.com/OpenTimer/OpenTimer with all the routing details (SpanMux instance etc ...)
<mithro> bblr
<tnt> mithro: No this doesn't output LUT and FF instances, it converts it to behavioral verilog.
<mithro> tnt: Check with elms on #symbiflow
<mithro> tnt: Well, vtr can output what your after (and the associated sdf timing file too....)
<tnt> Ah, thanks for the tip.
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<daveshah> tnt: icetime -o should work too
<tnt> daveshah: ah yeah, very close to what I need.
<tnt> genrated verilog seems to have minor issues though (like duplicate declaration of wires ...)
<daveshah> I'm not sure if this has even been tested with the UltraPlus, or even that much at all
<daveshah> But it's original intention was for OpenTimer integration
<tnt> Ah ok. I'll take a look at it to fix it up :)
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