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<Sprite_tm>
Hey guys, there seems to be a primitive to use the JTAG tap on an ECP5 in user mode (JTAGG).
<Sprite_tm>
Where would one find documentation for that? I've already scanned through the Lattice and prjtrellis docs and threw a few things at mr. Google, but I got nuttin'.
<daveshah>
There is no documentation, afaik
<daveshah>
Lattice consider it for internal use only (e.g. in the Reveal logic analyser), so someone would have to reverse engineer how to use it
<Sprite_tm>
Eh, I've got an hour, openocd and a LA... I can poke a stick at it, see what it does :P
<Sprite_tm>
Tbh, seems reasonably reasonable if I assume JTAGF is the same thing as JTAGG.
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<azonenberg_work>
daveshah: speaking of things that need to be reversed
<azonenberg_work>
if anybody has time (I've been too busy lately)
<azonenberg_work>
I would love to build a libscopehal driver for vivado chipscope
<azonenberg_work>
f/oss LA cores are all well and good but sometimes due to circumstances beyond your control you're stuck with a bitstream using the proprietary LA
<azonenberg_work>
The other thing i want is bridges, both ways, from jtaghal to the vivado cable server
<azonenberg_work>
So i can use any xilinx-supported proprietary jtag dongle from jtaghal over the network, or get vivado to talk to my board using a jtaghal backend
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