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<mkdir> hey
<mkdir> got the ice40, should be here tomorrw!
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<mkdir> what are some good tools for compiling verilog
<mkdir> to a bit file
<mkdir> open src preferred
<whitequark> mkdir: pretty much only yosys+nextpnr
<mkdir> are there any tools i can use for xilinx fpga and flash it with a different tool? currently I use WebPack ISE to compile my Verilog
<mkdir> and i flash with my other tool
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<zignig> managed to get a 19200 uart TX working on a Boneless-CPU, now for the RX
* zignig reaches for the LARGE hammer
<ZipCPU> zignig: Awesome! Did you manage to formally verify it as well?
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<zignig> hey ZipCPU , nowhere near it. it's running on nMigen in a tinyfpgaBX.
<zignig> just got it working, http://github.com/zignig/gismotron , it's CPU and peripherals at the python level.
<ZipCPU> It's gizmotron, but I see it now
<zignig> all gateware (in fact the entire universe) needs to be formally verified. small steps.
<zignig> stupid fingers :)
<ZipCPU> Go for it! ;)
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<zignig> with the nmigen-boards package I hope to have a portable 16bit cpu that can run on _all_ the ice40 and ecp5 boards.
<zignig> the Boneless-CPU with a uart weighs in at 599 4lut + RAM blocks, so it's tiny.
<zignig> my long term plan is to port ValentyUSB to nMigen and have the Boneless hand out any usb device that has a driver written.
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<whitequark> I'll finish verifying Boneless a bit later
<whitequark> I was quite busy getting nMigen usable in real world.
<whitequark> zignig: actually, 599 4-LUTs seems a bit high... I'm aiming for something like 300-400 ideally.
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<tnt> zignig: heh, somewhat similar to what I'm working on, exepct I'm of course using my own usb core and my own 16bit cpu :)
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<mkdir> is there a free verilog synthesis tool for Xilinx Spartan 6? ISE is a big boii
<tnt> mkdir: there is not a complete chain, no.
<tnt> (the 'synthesis' part I think works in yosys, but there is no place/route/bitstream generation so you'd still need ISE)
<mkdir> Ah I see so is ISE my only option then? I don't mind it, but man it's very fat. 25 gb extra needed on my VM
<mkdir> tnt, what does a synthesizer do? I thought it would turn the verilog into a bitstream
<mkdir> but I'm guessing not
<mkdir> now
<emeb> A lot of the fat in ISE is not needed for just doing Spartan 6 work.
<emeb> Most of it is libraries for parts you'll never use. I was able to trim an ISE installation down to fit on a 4GB SD card once, but it was only usable for one particular part family and only in one language.
<tnt> mkdir: synthesis turns verilog into a netlist of elements that exist in the spartan6. Kind of like the 'schematic' part. Then you need to actually place all those elements at specific sites in the fpga and route all connections between them.
<tnt> mkdir: and then you need to take the result of all of that into an actual binary file to send to the fpga.
<mkdir> ah ok
<mkdir> and i'm guessing no one has done that "backend" step?
<mkdir> seems like a cool project honestly
<mkdir> yeah emeb: I see, I like to call that bloatware
<emeb> mkdir: exactly so.
<mkdir> Thanks tnt, I get it now nextpnr does the place n route for ice40
<mkdir> so really it's the nextpnr that does not have compatibility with Spartan 6
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<Xark> emeb: Hello. I am playing around with your up5k_vga project. Is it expected to "fail timing" for the 40Mhz VGA clock (says "max 28.21Mhz)? I haven't made any modifications yet.
<emeb> Xark: yes - it always fails timing
<emeb> works nevertheless
<emeb> Xark: the timing failure is due to a "false path"
<Xark> emeb: Cool, just double checking. :D
<emeb> Xark: Theoretically that false path may be exercised if you try to run 6502 code from inside the Video RAM, so don't do that. :)
<Xark> emeb: Hehe, good to know. :)
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<Xark> emeb: I have a source 12Mhz clock, so hopefully 39.750Mhz is close enough for VGA...(and everything else will be a bit slower).
<emeb> Xark: Hard to say - some VGA monitors are pretty picky.
<Xark> emeb: Yeah...if I have issues with VGA "sync" then I will maybe fall back to 800x600@56Hz (that needs 36Mhz that I can get exactly from 12Mhz).
<emeb> Yep.
<emeb> I tried that mode on my monitors and they didn't like it - they only support modes w/ 60Hz vertical refresh.
<emeb> But it shouldn't be too tough to modify the timing parameters. They're all broken out in the vga source code.
<Xark> ...I was just thinking that also (having tried various modes in the past). :) There are other options (and pretty sure worst case 640x480 @ 25Mhz or so pixel clock will work).
<Xark> (But I like your 800x600...)
<emeb> Yeah. Gotta admit I was tempted to add an SI5351 programmable frequency chip in order to get the VGA rates exactly right. :)
<emeb> use one of the I2C IP cores on the up5k to talk to it...
<Xark> That would be great for exact VGA. I think I have one of those on a breakout board (but it would be awkward to use with this IceBreaker board).
<emeb> Those breakout boards are super-cheap on ebay - I've got one too.
<Xark> emeb: I was thinking of bodging together a PMOD for the audio circuit...I guess I could perhaps add it on to that.
<Xark> (I also notice one of my PS2 PMODs only uses "one row" - 6 pins)
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