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<tnt> ERROR: cell type '$_DFFSR_PPP_' is unsupported (instantiated as '$auto$simplemap.cc:467:simplemap_dffsr$779')
<tnt> huh ... never seen this before.
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<daveshah> tnt: will happen if you have a flipflop with both set and reset
<daveshah> *async set and reset
<daveshah> or an async load with constant
<tnt> daveshah: ok, good to know. Turned out to be a mismatched begin/end which ... ended up describing I have no idea what, but obviously something not synthesizable :p
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<tnt> yosys+nextpnr is too fast ... I don't have the time between `make prog` to grab the board and press the button to switch it to DFU ...
<tnt> first world problems.
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<etrig> I can work on that after I submit my pull request for flexnet licensing support
<tnt> etrig: \o/
<tnt> etrig: Don't forget memory usage too.
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<tnt> Verilog doesn't have the equivalent of 'step' in python ? like [15:0:2] ?
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