<azonenberg>
that's lut glitching, not pipe delay glitching
<azonenberg>
the pipe delay doesnt glitch
<azonenberg>
lol
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<sorear>
if you change both inputs to a XOR gate in the same cycle, you'll get a glitch even in standard cell…
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<azonenberg>
yeah i know, i just derped and thought i had done a direct output
<azonenberg>
used the wrong signal to the pin :)
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<mwk>
hm, anybody has a clue what is "TML" electrical standard?
<mwk>
it's an undocumented IOSTANDARD supported by spartan6, looks like a variant of TMDS
<tnt>
never heard of it
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<Dolu>
azonenberg_work : About java, a funny one is also the arithmetic. Byte | Byte => Int as result expression type XD
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<nats`>
ohhhh Dolu :)
<Dolu>
Hi nats` XD
<Dolu>
How things are going ?
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<ZombieChicken>
Is is possible to make an FPGA (or similar device) unusable if you feed it an incorrect bitstream?
<sorear>
it's *possible* but I've never heard of it being done by accident
<azonenberg_work>
ZombieChicken: Hard data point: I destroyed an xc2c32a with a carefully crafted bitstream full of short circuits in one-hot muxes
<ZombieChicken>
ty
<ZombieChicken>
so it pretty much has to be something intentional
<azonenberg_work>
i had to reverse engineer the bitstream, spend some time figuring out which lines to short
<azonenberg_work>
and it still took ten minutes to achieve a fatal result
<azonenberg_work>
pulling 150+ mA on a rail that should have never consumed more than about 5
<azonenberg_work>
Doing it by accident, while not impossible, is improbable
<ZombieChicken>
ty
<sorear>
so in a real application you'd probably trip an upstream current limiter first
<azonenberg_work>
Iffff you did the whole chip
<azonenberg_work>
yes
<azonenberg_work>
That being said, it's plausible that a single internal bus fight left long enough would blow out a single routing path or lut output or something
<azonenberg_work>
rendering the chip still usable but giving bad or inconsistent results for a single gate
<adamgreig>
wouldn't that be fun to debug
<azonenberg_work>
DRCing of generated bitstreams, to verify that you're not doing anything like that, is definitely a must for a production-grade toolchain
<sorear>
how much public intel is there about the DRC mechanisms on aws f1?
<TD-Linux>
you don't upload bitstreams to f1
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<azonenberg_work>
Yeah, they do some partial reconfig magic after compiling your design on their platform through some custom scripts
<azonenberg_work>
so i dont think it would be possible to generate an invalid bitstream
<azonenberg_work>
Going to guess they block the ICAP
<sorear>
I was under the impression f1 generated bitstreams using vivado on the same node that you have root over
<sorear>
the safety stuff seems to be largely angled at preventing *external* bus fights with the other components on the card / host