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<vup2>
would you be able to use the normal io's of the ecp5 with the output of the HMCAD1511? afaict they only go up to 800MHz
<whitequark>
HMCAD only goes up to 700
<vup2>
wait how do you get 1gsps at 8bit with 8 lvds channels at 700MHz?
<whitequark>
i think it has 16
<vup2>
what? am i totally blind? the datasheet only mentions channels {1,2,3,4}{A,B}
<whitequark>
oh, you are right
<whitequark>
good question
<whitequark>
vup2: hm, doesn't it transfer data on both edges?
<vup2>
ah right
<vup2>
but that means you can't use it with the normal ecp5 io's right?
<whitequark>
hm, i don't recall anything that would prevent it but i might be wrong
<whitequark>
aiui ecp5 has edge clocks that are phase locked to primary io clock but faster
<whitequark>
this is used for things like ddr and qdr
<vup2>
well i though the ecp5 io's can only do 400MHz and you would need 500MHz, no?
<whitequark>
lemme look at it
<daveshah>
ECP5 IO are 800Mbps max, edge clocks 400MHz max
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<whitequark>
that seems like a problem, yes :S
<daveshah>
Yup, some overclocking might be possible but I wouldn't rely on it
<vup2>
hmm too bad
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<tnt>
Heh neat, I can make USB work with just the HF_OSC :)
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<emeb>
Surprising that's stable/accurate enough for good USB
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<tnt>
emeb: atm it's just enumerating, so not too surprising. Packets are short.
<tnt>
For RX, I do clock recovery so it's pretty tolerant.
<tnt>
For TX and long packets I might need to allow for 'sub clock cycle' adjustement by accumulating the error and inserting/removing clock cycles from time to time.
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<emeb>
tnt: or you could do closed-loop frequency control on the HF_OSC.
<emeb>
Since there are tweaking bits available on the core.
<emeb>
Use the SOF timing similar to how the crystal-less USB on STM32F0x2 parts works.
<tnt>
emeb: yeah, I was planning to use the SoF to calibrate my accumulator for th tx 'ticks'.
<tnt>
I though about the HF tweaking but (1) might not be precise enough. (2) no idea if it's "glitch less".
<sorear>
how does fine adjustment for SB_HFOSC work? the aug2016 technology library PDF only documents a 2-bit (48, 24, 12, 6) control
<emeb>
sorear: daveshah found that there is an undocumented bus input on the HF_OSC input that is used to adjust the frequency over a fairly wide range in fine steps.
<sorear>
ah, found it in logs
<tnt>
"fine" is all relative. Also apparently non-monotonic which makes closed loop control "fun"
<emeb>
ugh - non-monotonic would be a bit of a nuisance.
<sorear>
wondering how this interacts with the factory trimming
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<tnt>
my oscillator seems to be only 3% too fast.
<tnt>
~ 24880 cycles between 2 SoF
<tnt>
(measuring a 24 MHz derived clock obviously)
<emeb>
that's not bad
<emeb>
I did a crude phase-noise test on the 48MHz output a while back - it's pretty noisy compared to even a cheap crystal.
<tnt>
sure but that shouldn't matter much for digital logic
<tnt>
I mean ... we _add_ jitter on purpose with spread spectrum clock gens :p
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<emeb>
heh
<emeb>
Just don't try to use the HF_OSC as a clock source for generating video - there was a noticeable difference in image stability with my NTSC generator.