<adamgreig>
The tag connect is okay for just flash or just FPGA but doesn't have enough pins to do both
<TD-Linux>
the flash writes fast enough that I usually don't bother uploading directly to fpga
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<kbeckmann>
prjtrellis-dvi - this is really nice! just tested it and got it working with the 640x480 setting. failing timing on higher settings for some reason. i set the FPGA_SIZE accordingly, and also tried to set the --speed 8 parameter, but am still getting failed timings (303 instead of 375 MHZ on clk_shift). is this a known limitation or is there some magic flag to nextpnr to help out with timing requirements? I
<kbeckmann>
built using the latest yosys/trellis/nextpnr
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<f003brv>
Any cool stuff?
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<tnt>
What's the easiest way to pass info from one bitstream to the next when using SB_WARMBOOT ? Basically when someone triggers the DFU runtime and 'reboots' into the DFU bitstream, I need to "know" it :/
<azonenberg>
tnt: hmmm
<azonenberg>
i could tell you for xilinx
<whitequark>
tnt: via a BRAM
<whitequark>
if you don't initialize a BRAM it retains contents
<whitequark>
there's no other way AFAIK
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<tnt>
yeah, bram is what I had too but I was hoping for easier. (need to gen a bitstream that doesn't initialize that 1 bram, also need to lock it at the same place in both dfu and app bitstream)
<tnt>
can you even select which bram to initialize independently ?
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<daveshah>
tnt: you can only pick a quadrant to initialise
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<tnt>
daveshah: yeah, rather rough choice :/ I think I'll just have the DFU image always boot in DFU mode and have a 'stub' default boot image that looks at the button and if it's pressed, reset to DFU image and if not, reset to app image.
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<whitequark>
daveshah: i'm curious, what's the deal with quadrants?
<daveshah>
whitequark: The iCE40 CRAM and BRAM init are both split up into 4 quadrants (aka) banks in the bitstream, each one is loaded individually, so you could e.g. exclude a BRAM quadrant from the bitstream (I think this is even a checkbox in iCEcube) and that quadrant would then persist re-configuration
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<whitequark>
daveshah: doesn't it have commands to initialize individual brams
<daveshah>
There is a "bank offset" feature, but I'm not exactly sure how it works or whether it could be used for this
<Bob_Dole>
I know those cheap chinese scopes are generally bad, but how bad? like how does the 30Mhz DSO338 (using an arm MCU and a 2 channel 100msps adc and connecting probes via trs rather than bnc) compare to 30+ year old used scopes on ebay?
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<whitequark>
there are 30+ year old used scopes on ebay that can do 20 Gbps
<whitequark>
(equivalent time, at least the scope i'm thinking of)
<Bob_Dole>
the best I've seen within 2-3x the price of the DSO338 are 50mhz scopes, but I've not been searching daily
<tnt>
Bob_Dole: really depends what kind of signal you want to look at ...
<Bob_Dole>
at least 1-10mhz digital logic well enough to diagnose any problems in assembly or design of a board, and likely some analog things in similar range. SolraBizna was interested in a LiFe inspired thing, needed to see if we could actually drive some things fast enough for still relatively low-speed connections.
<Bob_Dole>
LiFi*
<tnt>
any analog scope are pretty much useless to look at non repeating signals.
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<Bob_Dole>
I'm less qualified to narrow down uses of a scope and actually use it, than SolraBizna, but I'm the one with all the tools to assemble things.
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<azonenberg>
Bob_Dole: $60 is pretty wimpy as far as scopes go
<azonenberg>
A few hundred will get you something sane-ish like a ds1054z
<Bob_Dole>
There's a lot that could be bad about it, but with how much other stuff has improved I wondered if it would be able to at least do what it says it can at that price, and if the firmware and cpu could keep up.
<Bob_Dole>
aa newer review of the thing came up than when I was really looking at it. Still not really sure what is going on, it apparently does stutter/lag occasionally so the latter concern was something to worry about
<azonenberg>
Bob_Dole: So personally, if i wanted to build something cheap but still useful
<azonenberg>
i'd bolt a HMCAD1511 ($65 @ qty 1 on digikey) to a small FPGA and a gig-e PHY
<azonenberg>
maybe a very basic afe with some simple gain/offset control
<azonenberg>
That will give you up to ~100 MHz bandwidth, 1 Gsps on 1 channel, 500 Msps on 2 channels, or 250 Msps on 4 channels runtime adjustable
<azonenberg>
it's the same chip most of the low-end rigols use
<Bob_Dole>
neat, and useful info
<azonenberg>
The HMCAD1520 is pin compatible, about 50% more expensive, and lets you do 12/14 bit sampling for higher precision measurements
<azonenberg>
(at the cost of lower sampling rate)
<azonenberg>
I plan to build exactly this as an I/O card for my modular oscilloscope, but with relatively minimal effort you could bolt an ecp5 and ethernet onto the same front-end and get a standalone unit
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