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<SolraBizna>
if I want to implement USB on an iCE40, I basically have to use bank 3, right?
<daveshah>
None of the existing USB implementations use the differential receiver afaik
<whitequark>
USB isn't really differential anyway
<whitequark>
it's more like dual single-ended
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<TD-Linux>
SolraBizna, check out the tinyfpga and fomu usb implementations
<whitequark>
also, *run*
<whitequark>
do literally anything else that's in your power
<TD-Linux>
well I think putting a ftdi chip on your board might be worse
<TD-Linux>
if only barely
<whitequark>
it depends on what you're trying to do, really
<azonenberg_work>
Lol
<azonenberg_work>
Yes, USB1/2 is not differential exactly
<azonenberg_work>
There are four possible line states for the 2 wires
<whitequark>
it's more like differentially themed protocol
<azonenberg_work>
Three of the four states are used, the fourth is invalid
<azonenberg_work>
Lol
<whitequark>
tell me i'm wrong
<TD-Linux>
does any usb receiver work with a dc offset
<azonenberg_work>
it's also not even remotely dc balanced
<azonenberg_work>
whitequark: you know what's funny?
<whitequark>
TD-Linux: nope
<azonenberg_work>
TD-Linux: not to my knowledge with usb 1/2
<azonenberg_work>
usb3 is the pcie physical layer and should work fine with a dc offset on the SS pairs up to the voltage limit of the coupling caps
<whitequark>
afaiu the only thing differential signaling in usb 1/2 achieves is emi
<whitequark>
like it's not differential, it's balanced
<azonenberg_work>
Except for the SE0 symbols? :p
<TD-Linux>
back before I knew better I tried to use a USB webcam as rear view for a car
<whitequark>
it's mostly balanced.
<whitequark>
afaik you can implement an usb device that only looks at one of D+/D- for actual data
<azonenberg_work>
whitequark: is it just me, or is the 10baseT physical layer much less cursed than usb FS?
* SolraBizna
starts actually reading how USB signalling works and immediately recognizes that it's better to add a controller IC
<TD-Linux>
"it's differential and has crcs, should be fine"
<whitequark>
and has a separate SE0 detector
<whitequark>
loooool
<whitequark>
azonenberg_work: i'm not familiar
<azonenberg_work>
whitequark: 2.5V p-p differential manchester coded (so 20 Mbps raw signaling rate all the time, no bit stuffing or anything)
<azonenberg_work>
idles at differential zero (no power consumption) between frames
<azonenberg_work>
The 55 55 55 D5 preamble is literally a sync sequence for the rx cdr to lock to
<whitequark>
yes, of course it's vastly superior
<whitequark>
but i mean
<azonenberg_work>
incidentally in all future ethernet standards it's been INSIDE the other line coding, and totally vestigial
<whitequark>
~everything is vastly superior than the usb 1/2 physical laeyr
<azonenberg_work>
the clock would lock fine without it
<whitequark>
lol
<azonenberg_work>
and there is a separate start-of-frame symbol
<azonenberg_work>
but it's kept around because MACs all expect it at higher speed and inserting/removing the preamble when bridging betwen 10M and faster stuff is too much work
<azonenberg_work>
So its not like ethernet is 100% free of legacy BS
<azonenberg_work>
then TCP/IP made the mistake (IMO) of putting checksums in the header and not at the end
<azonenberg_work>
meaning you have to buffer a whole packet before you can send it
<whitequark>
azonenberg_work: if it was only ip checksum you could work around it with fragmentation
<SolraBizna>
okay, much better question now... what's the best way to add USB 1.1 host capability to a system whose main processor will be an iCE40-based soft CPU?
<azonenberg_work>
ip checksum is just headers
<azonenberg_work>
you can precompute that with minimal buffering
<whitequark>
oh, right
<SolraBizna>
(assuming I'm satisfying with waving my hand and saying "bring your own 5V")
<whitequark>
SolraBizna: what kind of host
<SolraBizna>
*satisfied
<SolraBizna>
a desktop computer, if you're satisfied with 90's performance
<whitequark>
no, i mean, what devices do you want to accept
<whitequark>
arbitrary?
<whitequark>
usb keyboards/mice?
<TD-Linux>
luckily as bitrate goes up but MTU stays the same the checksum location is less and less of an issue
<SolraBizna>
USB keyboards as a minimum, but arbitrary devices with arbitrary amounts of software work ideally
<whitequark>
that's tough
<whitequark>
really tough
<TD-Linux>
ice40 is a bit small for that
<TD-Linux>
do you have a rtos with a usb host stack
<SolraBizna>
my original plan was to put the bare minimum to interface with the USB physical layer on the iCE40, and then fill the gap in software
<SolraBizna>
not yet, but I will
<SolraBizna>
(actually, my original plan was not to have USB on this iteration at all, but someone kept pestering me to add it)
<SolraBizna>
at this point, I'm mainly interested in making it so that it could be made to work with arbitrary amounts of software/firmware tweaking "later"
<SolraBizna>
so, just connecting D+/D- pins directly to the FPGA and saying "I'll fix it in Verilog" would have been fine if USB physical layer weren't so evil
<azonenberg_work>
SolraBizna: well i would be very interested in you using my protocol decoders in scopehal to debug it
<azonenberg_work>
you can totally do that
<azonenberg_work>
but they have to be separate single ended lines
<TD-Linux>
you might need pullups(?) but yeah just run two pins in
<whitequark>
it costs $16@1, but not having to deal with usb insanity is priceless
<SolraBizna>
$16 is less than the maximum I would pay not to deal with USB insanity
<azonenberg_work>
FWIW, on digilent devkits
<SolraBizna>
That looks completely perfect
<azonenberg_work>
they drop on a usb capable PIC attached to the usb host ports
<azonenberg_work>
then speak PS/2 to the fpga
<whitequark>
well that or ULPI
<azonenberg_work>
(for keyboard/mouse, i guess nothing else supported?)
<whitequark>
but ULPI is more tricky although it gives you HS
<SolraBizna>
HS would be total overkill for this iteration, given... well, actually, I don't know how fast the fastest iCE40 RISC-V cores ended up being
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<futarisIRCcloud>
SolraBizna: MAX3421E is another option.
<whitequark>
but then you have to use a maxim chip
<SolraBizna>
but I already finalized the schematic, fabricated the board, assembled and tested and shipped the product...
<SolraBizna>
the USB controller is going into a gaping hole where a parallel SRAM used to be, so the SL811HST is a better fit than an SPI thingy
<tpw_rules>
what kind of desktop computer?
<tpw_rules>
like capabilities?
<tpw_rules>
windows 95 for risc-v?
<Bob_Dole>
probably more like a mac plus with a 68040