<mithro>
tnt: There is a wireshark decoder floating around
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<tnt>
mmm ... I'm looking at the Vex RiscV and I'm seeing doubled up writes ...
<tnt>
oh wtf, it's not even jumping at the right addresses.
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<tnt>
the _Lite variant behaves much more sanely than the _Min variant it seems.
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<tnt>
someone is doing github cleanup :)
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<tnt>
Anyone has experience with spinalhdl ? I'm trying to rebuild the VexRiscv-verilog with different settings in src/main/scala/vexriscv/GenCoreDefault.scala but it seems to completely ignore my changes :/
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<daveshah>
tnt: what command are you running?
<daveshah>
I've used `sbt "runMain vexriscv.GenCoreDefault --externalInterruptArray=true --csrPluginConfig=linux-minimal"` to regenerate Verilog successfully (this was the Linux variant)
<tnt>
make VexRiscv_Min.v
<tnt>
I can even put a syntax error in ./src/main/scala/vexriscv/GenCoreDefault.scala and it won't care ...
<tnt>
If I erase my ~/.sbt directory at least it will trip on the syntax error but it still doesn't look like it's applying the requested config changes.
<tnt>
it does rebuild the verilog ... but ignores my changes
<daveshah>
I think there are other VexRiscv-verilog repos though
* tnt
slaps himself ...
<tnt>
permission issue ... it couldn't orverwrite the existing VexRiscv_Min.v and it wasn't printing any error or warning and just silently failing ...
<whitequark>
tnt: glasgow has fx2 emulator gateware
<tnt>
whitequark: ?
<whitequark>
19:00 < tnt> mithro: yeah, I read that. but my interest was not really to implement it in a fx2 :) Just a working emulator would have been a good reference.