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<emeb>
tnt: do you have any plans to push further on your riscv-usb project? I'm curious to try some riscv & usb stuff and that seems like a promising place to start.
<tnt>
emeb: yes ATM I'm writing a USB <-> E1 adapter and this project is the base for it.
<tnt>
But the USB core itself is pretty much done. The 'software' stack is a bit ... minimal, but the hw itself works fine.
<tnt>
I did test isochronous streaming with it for instance.
<emeb>
Oh, cool.
<emeb>
I think I've pushed that 6502 project about as far as I want to and I'm starting to get annoyed w/ 8-bit assembly, so I want to try something bigger... :)
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<tnt>
emeb: hehe. I also have an experimental 16-bit cpu and matching c compiler if you don't want to jump to 32b dirctly.
<emeb>
tnt: haha - baby steps then. I may take you up on that if if the riscv is too much power for me. :)
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<tnt>
At least the sim models from lattice are correct for the IO blocks.
<tnt>
(at least I think)
<daveshah>
I think the icecube models might be correct, the Radiant one which I looked at definitely models clock enable incorrectly
<tnt>
daveshah: really? I'm looking at the radiant ones.
<daveshah>
Which one?
<tnt>
IO_SIM.v
<tnt>
it even has the "wrong" version commented out "//assign inclk = (inclk_ & CLOCK_ENABLE);" and then just below the version with a synchronizer.
<daveshah>
Ah, I was looking at IOLOGIC.v
<daveshah>
Which IOL_B, which I think is the Radiant ddr primitive, instantiates
<tnt>
Oh, might be.
<tnt>
I'm assuming IO_SIM is what's used in the SB_IO model ... but that one is encrypted
<daveshah>
They encrypted all the SB_ models in Radiant even though they are unencrypted in icecube
<daveshah>
I'm pretty sure this is a hack to stop some part of the Radiant flow seeing them for some reason (as it doesn't use them) rather than genuine security