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<eddyb>
daveshah: so I was looking around for FPGAs with lots of IOs and I stumbled over MachXO3, which I don't think I've seen much discussion on before. AFAICT the bitstream format hasn't been reverse engineered yet, I just wanted to double-check that that's correct
<daveshah>
Some work has been done on MachXO2 by cr1901_modern and AndresNavarro
<daveshah>
I think MachXO3 is quite similar to that
<daveshah>
both have some similarities to ECP5 too
<OmniMancer>
I think I also have a MachXO2 board around somewhere
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<eddyb>
huh, ECP3 goes up to 586 IOs, XP2 up to 540, XO3 up to 384, and ECP5 only up to 365. do better serdes mean less incentive to have a ton of IO pins?
<eddyb>
although I guess 365 is still a lot, maybe they just went overboard with the ECP3
<daveshah>
The ECP3 was much more of a premium product
<daveshah>
Lattice has since moved to focusing on cost/die size for the ECP5
<gruetzkopf>
ECP3 would be fun to have
<eddyb>
I'm not even sure what you'd use 500+ IOs for other than external DRAM
<whitequark>
hundred of ADCs with parallel buses
<eddyb>
although I suspect azonenberg already has a ALLCAPS name for a board idea that uses such a monster
<whitequark>
or like
<whitequark>
a 48-port switch with GMII interface
<whitequark>
or a board driving a dozen parallel RGB displays
<eddyb>
right, I just don't know why you'd hook up that many things to one FPGA, at some point it's probably cheaper to use several smaller ones
<whitequark>
and you might want to put like thirty of these on a board
<tpw_rules>
but at what cost???
<whitequark>
where you're going with that board, cost is not a concern
<whitequark>
it's usually backplanes for defense
<tpw_rules>
""
<eddyb>
so Xilinx kinds confuses me, but looking closer at it, 7-series are all the Foo-7 product lines? and all of them could be handled by Project XRay?
<tpw_rules>
!track defense
<whitequark>
wrong channel lol
<tpw_rules>
:P
<daveshah>
eddyb: yeah, pretty sure the logic tiles and stuff are all the same
<daveshah>
just different timing & some IO/SERDES differences
<daveshah>
the US/US+ parts are different but the tools could be re-used
<eddyb>
ugh defense is even worse than spaceflight isn't it
<daveshah>
think phased array radar for a high-pin-count application
<whitequark>
the only thing xilinx could imagine for their largest US+ FPGA is an over the horizon radar
<eddyb>
oh hey phased arrays, unlike active missile controllers, could be a civilian/amateur project :D
<whitequark>
they are regulated
<whitequark>
so if you make one that's too large you could get v&d
<eddyb>
the "US" stands for "United States (defense)", right?
<whitequark>
no
<tpw_rules>
i want to put one of them on my car and make an overlay that displays the speed of all the vehicles in front of me
<whitequark>
ultrascale+
<whitequark>
code word for ridiculously large and overpriced
<whitequark>
a few k$ per FPGA
<whitequark>
m-labs uses some of the regular ultrascale ones
<eddyb>
(I should add the interrobang to my layout just so I can disambiguate me being dumb from me making bad jokes)
<eddyb>
whitequark: was thinking more "indoor object tracking" more than "over the horizon" btw :P
<eddyb>
but if you were using all of those IOs for external memory, you could always add more to increase your throughput, right? oh but if you're memory-bound you might be able to distribute your workload anyway
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<adamgreig>
it's always a bit terrifying talking to defence types about their fpgas
<adamgreig>
"you have _how many_ JESD204B lanes???"
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<cr1901_modern>
While AndresNavarro got me to get off my rear end and bring my copy of prjtrellis up to date, he seems to have not been around the past few weeks
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<mietek>
i have a problem driving a 5V active-low signal from a 3.3V Teensy 3.6
<mietek>
i was naively hoping that resistor-based voltage division would work both ways
<mietek>
the horizontal resistors are 17.4 kΩ; the vertical ones are 33.2 kΩ
<mietek>
for a 5 V _input_ voltage, this was supposed to give 3.281 V _output_
<mietek>
but i guess i need to do something different for voltage multiplication
<mietek>
any hints?
<cr1901_modern>
In practice you _probably_ don't need the vertical ones and everything will still work just fine- input impedance of teensy pins will provide the rest of the voltage division
<cr1901_modern>
You can't get voltage multiplication using resistors alone
<mietek>
please note the waveforms indicate that i’m not driving the lines low enough
<daveshah>
Is there a pullup on the other side?
<daveshah>
The horizontal resistor will form a divider with the pullup when driving low
<mietek>
cr1901_modern: my circuit is probably totally wrong for the CLR and CLK lines
<mietek>
cr1901_modern: i’m supposed to be driving these lines from the 3.3 V side
<mietek>
when idle, CLR and CLK are supposed to be high; then, when signalling, they are supposed to be pulled low from the 3.3 V side
<cr1901_modern>
I'm a bit too fried to give detailed advice right now, sorry :(
<mietek>
daveshah: not sure which side you mean, but the answer is no in either case; there are no pullups connected to either side of CLR or CLK right now; the socket on the 5 V side has been left disconnected for the measurement
<mietek>
cr1901_modern: no worries, thanks
<mietek>
also please talk to me like i’m a bright 5 y.o.
<mietek>
because i really know nothing about electronics
<tnt>
don't worry, we got that as soon as you said you hoped a resistor divider would work both ways. :p
<mietek>
on my input line (DIN), i’m seeing an echo of my outputs (CLK visible here, but CLR also)
<mietek>
and it looks like sometimes it spikes a bit more
<mietek>
the echo spikes
<mietek>
what could be the reason for the echoes?
<mietek>
this is using an internal pullup for the input line
<mietek>
but the input voltage levels at about 2.78 V
<mietek>
should i add an external pullup?
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<azonenberg>
eddyb: Re 500 IOs, its not all that hard to use up with big stuff
<azonenberg>
i had a 484 ball fpga planned for LATENTRED and didn't have enough IOs (285 GPIOs out of 484 total balls) so i had to add a second smaller FPGA for I/O expansion
<azonenberg>
but i was lucky with the partitioning, i had a lot of slow GPIO type stuff for status LEDs, resets, i2c sensors, and such where performance did not matter at all
<azonenberg>
and all of the SGMII and 10Gbase-R lanes hang off the main fpga
<azonenberg>
LATENTORANGE will need to be a bigger fpga because of the transceivers
<whitequark>
what's LATENTYELLOW?
<azonenberg>
I could get 28 transceivers in an 900-ball XCKU9P which would be enough for 2x 40GbE and 20x 10GbE, but that's also a $2K FPGA not supported by free tools
<azonenberg>
Which is a potential problem (but by that point i'll probably have the budget for a vivado seat)
<azonenberg>
whitequark: tentatively? some kind of routing/firewall appliance
<azonenberg>
maybe something that can do port-based firewalling, nat, ipv4/v6 routing, etc at 40GbE line rate with formally verified isolation performance?
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<eddyb>
heh, reminds me edef wanted to do something fancy with IPv6
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<edef>
hi i heard "routing, etc, at 40GbE line rate"
<eddyb>
open port, sesame
<edef>
:D
<azonenberg>
edef: that's several projects down the road
<azonenberg>
LATENTRED comes first which will be a relatively cheap commodity 1G switch with 10G uplinks
<azonenberg>
And before THAT i have to finish FREESAMPLE, which is close to ready to send to fab but is held up because the project budget is being spent on construction so i havent been working on it the last week or so
<edef>
good, my need for anything 40GbE is also a while down the road
<azonenberg>
i have some 40G hardware but havent needed it yet
<azonenberg>
none of it is in service
<azonenberg>
well ok there is a 40G nic in this computer
<azonenberg>
but its not plugged into anything
<whitequark>
where do you even get a 40G NIC
<MicroHex>
probably surplis infiniband hardware
<azonenberg>
amazon? newegg?
<MicroHex>
and yes, it's pretty common, just not cheap
<azonenberg>
amazon has the X710-DA2 for $218
<azonenberg>
thats two 40G QSFP+ interfaces on a pcie 3.0 x8 card
<azonenberg>
intel chipset with good linux support
<whitequark>
huh
<azonenberg>
somewhat annoyingly, it can operate one interface in 4x 10G mode but you can't use the other port if you do that
<whitequark>
is QSFP+ backwards compatible?
<whitequark>
with SFP
<azonenberg>
QSFP+ is physically incompatible with SFP+, it has four lanes instead of one
<azonenberg>
"quad SFP"
<whitequark>
i was wondering if they kept the compatibility somehow
<azonenberg>
most common QSFP+ optics actually are basically four SFPs in one
<whitequark>
like SATA Express did
<whitequark>
wait
<azonenberg>
with four lasers, four photodiodes, and connected to an 8-fiber connector
<whitequark>
is that just four bonded 10 Gbps channels?
<azonenberg>
although they make WDM optics that use a standard duplex fiber with four lasers
<azonenberg>
40Gbase-SR4 is exactly that
<whitequark>
oh
<azonenberg>
Most 40G hardware can split the four links out into four 10G lanes
<azonenberg>
with a splitter cable that has a MPO connector on one end and four LCs on the other
<whitequark>
wait, I just realized that instead of that I can use... Thunderbolt
<whitequark>
for all my practical needs
<azonenberg>
The issue in this case is that the 710 NIC only has four macs
<azonenberg>
so you can have two lanes on each port in 10G mode and two unused
<azonenberg>
four lanes on one port in 10G mode and the other port unused
<azonenberg>
or all lanes of both ports in 40G mode and the other two MACs unused
<azonenberg>
There's no way to use it as eight 10G ports
<azonenberg>
CFP is a rarely used extension that is ten 10G lanes for 100GbE
<azonenberg>
More common for modern 100GbE is QSFP28 which is a QSFP+ compatible optic with four 25Gbps lanes instead of four 10G
<azonenberg>
That's what my VCU118s have on them, but they're only loaded with 40G optics so you can't run them at 100G without buying more expensive optics
<azonenberg>
(i saw no reason to buy 100G optics when the PC only had a 40G card)
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<adamgreig>
has anyone used ptp much? especially over commodity switches, i.e. not actual clocks?
<adamgreig>
mostly just wondering how much of a bad idea it is
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<azonenberg>
matthiasm in ##fpga has done a fair bit of 1588
<azonenberg>
i havent used it much myself
<adamgreig>
is that like ##openfpga's evil twin
<azonenberg>
It's for fpga tech in general, this channel is specifically for f/oss tools
<azonenberg>
But they arent exclusive to proprietary tools
<whitequark>
##closedfpga
<adamgreig>
all the bitter redditors could hang out there
<emeb>
Simple 4-voice sigma-delta sound generator for 6502 system working - 0-32kHz frequency range, saw/square/triangle/sine/noise wavforms and volume control. First time using the ice40 DSP cores from within yosys - '-dsp' command option deployed successfully. -> https://github.com/emeb/up5k_basic/blob/master/src/snd.v
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