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<emeb_mac> sigh - this spi flash erase/write thing is really becoming annoying.
<emeb_mac> had it working fine last week, then it seems to have stopped working at some point. I've even tried reverting my code back to last weeks revisions and it still didn't get things working.
<emeb_mac> this afternoon I built up a new board but that didn't fix it either.
<emeb_mac> I'm sure that when I finally figure it out I'll be slapping my forehead, but until then it's a big mystery.
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<SolraBizna> turns out eeschema comes with integrated SPICE now... except I can't get it to successfully simulate the simplest circuit
<SolraBizna> ("the simplest circuit" being a single resistor with a DC voltage applied)
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<SolraBizna> ← this circuit is so simple even I can work it out; I can't figure out what eeschema's ngspice integration hates about it
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<vup> just a guess, but maybe it needs a valid reference designator for the resistor?
<SolraBizna> It also fails with R0 as the reference
<daveshah> Might also need the negative of the voltage source connected to ground
<daveshah> This will probably be a singular matrix otherwise
<SolraBizna> if I add an earth symbol, to the negative terminal, the error message changes from `Warning: singular matrix: check nodes net-_r0-pad2_ and net-_r0-pad2_` to `Warning: singular matrix: check nodes earth and earth`
<SolraBizna> someone on the Internet said that this happens when you have zero-impedence connections between voltage symbols, except... it really seems to me that this circuit can't possibly have one
<SolraBizna> well, I shouldn't call that an error message since it's a warning message, but it does seem to be the source of the problem
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<SolraBizna> ... it works perfectly if I use a different kind of ground symbol
<SolraBizna> I can't find a more usual source symbol (other than this one GND symbol) that still works
<SolraBizna> well, at least it does work
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<SolraBizna> it feels like everything was different than it was 25 years ago, when I first learned how to make and read circuit schematics
<SolraBizna> s/was/is/
<SolraBizna> is it a USA vs. rest-of-world thing?
<SolraBizna> also, now I feel really old, that's a big number of years...
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<togemet2> Oman Archive. Anyone have it? I'm not interested in the 150mb compressed file that only contains half.
<tnt> Mmm ... I might have burned something on my icebreaker :/
<keesj> ice & fire
<tnt> Mmm, no idea what the issue was, but seems fixed now.
<tnt> The Uart TX line (from iCE40 to FTDI) had a very low swing. From ~ 1.5v to 2.25v instead of 0-3.3. Like if something was forcing it mid rail.
<whitequark> sounds like a bus conflict
<whitequark> maybe the FTDI was in the wrong mode?
<whitequark> not UART
<tnt> well I had minicom open and "most" characters wold actually go through ...
<tnt> Also, what's weird is it was 'centered' around the mid-rail so that's a weird bus-conflict.
<tnt> Now when I disconnect the ftdi pin, it does for some reason, float to 1.7v :/
<tnt> no idea if that's normal (like they have some input circuitry or something that bias it midrail)
<gruetzkopf> that'd be a very strange point to bias
<tnt> well if you have a schmidt trigger input and you want to allow ac-coupled input ...
<tnt> (no idea _why_ a ftdi would have that ...)
<whitequark> that's one half of 3.3...
<whitequark> hrm
<tnt> yeah, it's definitely weird. Also no idea what fixed out. (although I lifed a pad of the PCB trace jumper/blob link when debugging this and had to replace that whole trace with a bodge wire so maybe I removed a short or something).
<tnt> I don't have another board to compare the idle / floating levels thogh.
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<keesj> I think following is a good start to get someting out of simulation kicad
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<whitequark> azonenberg_work: btw regarding your screwdriver thingie
<whitequark> i no longer have contacts of reliable cnc people, unfortunately
<whitequark> i'll tell you when i do again
<somlo> ZipCPU: if I need to have an AXI4 master connect to a Wishbone slave, would be exactly what I need (from the perspective of master/slave gender/polarity)?
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<ZipCPU> somlo: The AXI4 master -> WB slave is one of those projects that is still "under construction". For all the work I've put into it so far, I haven't (yet) gotten to success.
<ZipCPU> However, there is an AXI-lite to WB converter within that repository
<ZipCPU> Check out: and its submodules, axilrd2wbsp.v and axilwr2wbsp.v
<ZipCPU> Those should be good enough to get you where you need to go
<ZipCPU> If your wishbone peripheral will never stall, and always return a value in one clock, then you can try the demo-AXI-full module I've been working on. It's passed its formal proofs, so should be good to go for you:
<somlo> ZipCPU: thanks for the pointers!
<somlo> Although, my AXI4 master device is *not* "Lite", and utilizes bursting...
<ZipCPU> How about your wishbone?
<somlo> the wishbone side is LiteX :)
<ZipCPU> Looks like litex is implementing WB classic, not WB pipelined ...
<ZipCPU> With WB classic, it won't matter if you are bursting or not ... the WB side won't support more than a single ongoing operation at a time
<ZipCPU> Also, it's not too hard to convert from WB-pipelined to classic, but it does require a register or two along the way.
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<somlo> at this point I don't care about efficiency or performance, I just want to get two devices talking to each other :) If *that* works, I'll worry about optimizations afterwards...
<ZipCPU> You'll need a pipeline->classic converter. That's *really* easy to build, just not something that I have as of yet.
<ZipCPU> (I might have it by tonight, if I don't get distracted)
<somlo> Even if you do, that is guaranteed to be sooner than I could make it happen :)
<somlo> * get distracted, I mean :)
<somlo> I just slogged my way through the AXI4 spec (skimming here and there, occasionally), but I haven't thoroughly read through the Wishbone spec, so I only have a vague guess as to the difference between "pipelined" and "classic"...
* somlo followed link to wbspec_b4.pdf, might as well read it between now and tonight :)
<ZipCPU> Want to see the difference in one slide?
<somlo> ZipCPU: sure, if you have a handy link!
<ZipCPU> Sorry, two slides. Check out slides numbered 26 and 27 from this presentation:
<ZipCPU> Slide 26 represents WB classic (ignore the Wishbone B4, Pipeline mode comment at the bottom)
<ZipCPU> Slide 27 shows what you can do with pipelined mode
<somlo> oh, it's kinda like bursting in AXI, except you're also sending each address value explicitly rather than have the other end increment a counter
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<somlo> which in theory means you could be jumping around the address space rather than go linearly (with optional wrap-around) :)
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<ZipCPU> somlo: the other issue is that WB classic requires tearing down the bus before you can create another request
<ZipCPU> somlo: Here, try this: That should at least get you close to a proper WB pipelined to classic bridge
<ZipCPU> Since I haven't formally verified it, I can't be certain that it works, but you should at least get an idea from the logic shown how much logic would actually be involved in building such a bridge.
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<somlo> ZipCPU: says "not found", but there's a "wbp2classic.v" file in the wb2axip repo; will the topology be something like AXI4Master <-> ? <-> wbm2axisp <-> wbp2classic.v <-> LiteX
<somlo> both sides of the "?" are axi *master*, so I basically need something that acts as an axi slave on one side, and wishbone master on the other
<ZipCPU> somlo: You should be able to get something that acts as an AXI-lite slave. There are plenty of non-open AXI->AXI-lite bridges available
<ZipCPU> You should then be able to go from AXI-lite to WB-pipelined via axilite2wbsp.v
<ZipCPU> The "cheat" sheet for understanding my names is that modules named X2Y are bridges where a master of bus type X can connect to a slave of type Y
<ZipCPU> The core you want, to go from AXI full to WB-pipelined would be axim2wbsp.v. That's the core that doesn't (yet) work
<ZipCPU> So the topology should be: AXI4Master -> AXI4-lite -> axlite2wbsp -> wbp2classic
<somlo> got it, thanks!
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