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<Cerpin>
Hi, going to toss this in here once more (code in a bit, once I've cleaned it up a little): Is there any reason a reg with both packed and unpacked dimensions would not be added to a trace generated by Verilator?
<Cerpin>
I have had verilator add it in one case, and in the other two not
<Cerpin>
(I am using the testbench template class from "taking a new look at verilator", and have simulated about 5 components otherwise successfully this way)
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<Cerpin>
Yeah, they aren't showing up in the ChgThis-whatever function either
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<Cerpin>
nvm, just found the option for max trace width!
<Cerpin>
3Err, depth too, but yes
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<tnt>
Cerpin: yeah, I'm not familiar with verilator specifics but usually it's done to avoid the whole content of all memories exported in the trace ... which would be huge.
<Cerpin>
Yup, that makes sense
<Cerpin>
Just have smallish memories and short trace in this case and wanted it
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<tnt>
"ERROR: Bel 'X18/Y31/io0' of type 'SB_IO' is not valid for cell 'e1_rx_I.phy_I.rx_lo_I' of type 'SB_IO'"
<tnt>
Well that's just such a clear error.
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<bubble_buster>
love when I accidentally try to add a memory array to modelsim waveform and modelsim just crashes
<pie__>
Type :ok_hand: Safety :ok_hand:
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