##openfpga on 2019-04-30 — irc logs at freenode.irclog.whitequark.org

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18:08 <SolraBizna> I fell asleep last night after adding a bunch of pull resistors to my schematic, but before connecting them to VCC.

18:08 <SolraBizna> I nearly signed off on this sheet without noticing.

18:09 <SolraBizna> Moral: Don't do EE work at 5AM.

18:10 <sorear> you can pull to ‘z right? :p

18:10 <SolraBizna> lol

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19:51 <kervel> hi @elms , thanks for your answer to my question yesterday. i lost my IRC connection but found your answer in the logs. i tried it and it works.

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20:45 <azonenberg> Lol

20:45 <azonenberg> SolraBizna: i would say moral is to run ERC before signoff

20:45 <azonenberg> (and go through a proper design review before making the board)

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22:11 <SolraBizna> This is a step, and likely would have caught that even if I hadn't, but still, it's a better story that way

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