Thorn has quit [Ping timeout: 250 seconds]
forrestv has joined ##openfpga
sxpert has joined ##openfpga
balrog has joined ##openfpga
balrog has quit [Ping timeout: 246 seconds]
balrog has joined ##openfpga
azonenberg_work has joined ##openfpga
dj_pi has quit [Quit: Leaving]
balrog has quit [Ping timeout: 255 seconds]
balrog has joined ##openfpga
unixb0y has quit [Ping timeout: 245 seconds]
<mossmann> 4
azonenberg_work has quit [Ping timeout: 245 seconds]
balrog has quit [Ping timeout: 246 seconds]
unixb0y has joined ##openfpga
balrog has joined ##openfpga
balrog has quit [Ping timeout: 246 seconds]
unixb0y has left ##openfpga ["part"]
balrog has joined ##openfpga
emeb has quit [Quit: Leaving.]
rohitksingh has joined ##openfpga
rohitksingh has quit [Remote host closed the connection]
gsi__ has joined ##openfpga
gsi_ has quit [Ping timeout: 246 seconds]
Bike has quit [Quit: Lost terminal]
rohitksingh_work has joined ##openfpga
_whitelogger has joined ##openfpga
azonenberg_work has joined ##openfpga
Thorn has joined ##openfpga
zem has quit [Ping timeout: 246 seconds]
zem has joined ##openfpga
m4ssi has joined ##openfpga
Thorn has quit [Ping timeout: 245 seconds]
<_whitenotifier-1> [Glasgow] whitequark commented on issue #118: Improve ESD immunity - https://git.io/fjIqf
<_whitenotifier-1> [Glasgow] whitequark commented on issue #68: Expose on-board I2C for accessories - https://git.io/fjIqt
<_whitenotifier-1> [Glasgow] whitequark commented on issue #68: Expose on-board I2C for accessories - https://git.io/fjIqO
emeb_mac has quit [Ping timeout: 255 seconds]
<_whitenotifier-1> [Glasgow] marcan commented on issue #118: Improve ESD immunity - https://git.io/fjImv
Thorn has joined ##openfpga
OmniMancer has joined ##openfpga
futarisIRCcloud has quit [Quit: Connection closed for inactivity]
eightdot has quit [Ping timeout: 250 seconds]
Asu has joined ##openfpga
<_whitenotifier-1> [Glasgow] whitequark reopened issue #89: Use SB_GB_IO instead of SB_IO+SB_GB - https://git.io/fjvFD
unixb0y has joined ##openfpga
cr1901_modern1 has joined ##openfpga
cr1901_modern has quit [Ping timeout: 258 seconds]
cr1901_modern1 has quit [Quit: Leaving.]
cr1901_modern has joined ##openfpga
<_whitenotifier-1> [Glasgow] whitequark commented on issue #89: Use SB_GB_IO instead of SB_IO+SB_GB - https://git.io/fjIsr
wpwrak has quit [Ping timeout: 246 seconds]
wpwrak has joined ##openfpga
<_whitenotifier-1> [Glasgow] whitequark commented on issue #89: Use SB_GB_IO instead of SB_IO+SB_GB - https://git.io/fjIGL
<_whitenotifier-1> [Glasgow] whitequark commented on issue #89: Use SB_GB_IO instead of SB_IO+SB_GB - https://git.io/fjIGZ
Sprite_tm has joined ##openfpga
<Sprite_tm> Hi all... Quick (I hope) question: I'm developing using a Yosys/nextpnr/prjtrellis tool suite for the Lattice ECP5 series.
<daveshah> Hi!
<Sprite_tm> Now, I've coded up a nice cache for my CPU. Unfortunately, the tools insist on stashing the bits for the cache in standard Trellis flipflops, not in BRAM.
<Sprite_tm> If I understand corrctly, the tools should be able to infer that stuff can be placed in BRAM and I'm just doing something terribly wrong, right?
<daveshah> Yes
<whitequark> what's your verilog?
<Sprite_tm> Erm, lemme upload it somewhere... sec.
<Sprite_tm> http://j0h.nl/Y8gB <- there
<Sprite_tm> Derp, wrong file...
<Sprite_tm> http://j0h.nl/YskB <- that's the one.
<Sprite_tm> I can imagine the tag memory and the flags memory don't make it into BRAM, as they're abused a fair bit, but I'd expect at least the main cachedata to end up there... It's a simple 32-bit wide memory, and I only read and write it in clocked blocks...
<Sprite_tm> Also, I would not be surprised if it's something silly I did... I don't have that much experience with Verilog yet.
Asu has quit [Ping timeout: 245 seconds]
Asu has joined ##openfpga
<whitequark> Sprite_tm: that memory has two read and two write ports
<whitequark> line 150-153 and line 214 are the two write ports
<whitequark> that's not synthesizable
<Sprite_tm> Ah, huh, both are clocked by clk and they're not exclusive.
<Sprite_tm> I thought yosys could figure that out :P
<whitequark> oh wait
<whitequark> that IS synthesizable for ECP5
Asu` has joined ##openfpga
<whitequark> since it has true dual port RAM
<daveshah> Yosys can't do mixed ports
Asu has quit [Read error: Connection reset by peer]
<Sprite_tm> mixed ports?
<daveshah> Ports that both read and write
<Sprite_tm> Thanks for taking the time to look at this, btw, I do appreciate it.
<Sprite_tm> FYI: data point: if I comment out the always block around 214, it still doesn't use bram.
<daveshah> There is also a known bug where memory accesses are deeply embedded in nested `if`s
<Sprite_tm> Ah, that may be the thing.
<Sprite_tm> Hm, guess I'm better off making the main cache mem its own module... that way I can at least control how it gets synthesized better.
<Sprite_tm> Thanks you all, this should allow me to continue for now.
Asu` has quit [Quit: Konversation terminated!]
<tnt> Sprite_tm: tbh in general I always find it better to isolate memories in separate modules. Write it in verilog and see if that works out but at least that make it easy to replace with instanciation for the numerous cases where inferring fails to produce what's needed.
rohitksingh_work has quit [Read error: Connection reset by peer]
<Sprite_tm> tnt: Yeah, I also came to that realization just now... I have absolutely no way of figuring out (aside from asking the wise people here) of figuring out why it doesn't want to put it in bram... it's easier when it's just in a submodule I'd think.
<whitequark> Sprite_tm: yosys writes a detailed log file
<whitequark> that says why noto
<tnt> Sprite_tm: sometime you can figure it out in the log file.
<Sprite_tm> Hehe, if you can *find* it :P
<Sprite_tm> I think I went through the log files, but probably missed the line.
<tnt> but tbh ... when it fails to do it most of the time I can't finish the synthesis because it crashes with lack of memory trying to create hundreds of thousands of FFs ...
<Sprite_tm> Yeah, I think having only a small cache saved me there... although I now probably know why synth time went up from one to ten minutes :P
<whitequark> there should be an option that forbids creation of FF RAM
<Sprite_tm> Btw, is it possible to pass the file for readmemh to a module in a parameter or something?
<tnt> yes as a param.
<Sprite_tm> And you guys said Yosys can't infer ram with two read-write ports yet, right? Should I fall back on instantiating primitives for that?
<Sprite_tm> Aah, I was looking for something like that, thanks.
rohitksingh has joined ##openfpga
<_whitenotifier-1> [Glasgow] enjoy-digital commented on issue #89: Use SB_GB_IO instead of SB_IO+SB_GB - https://git.io/fjIca
<_whitenotifier-1> [Glasgow] whitequark commented on issue #89: Use SB_GB_IO instead of SB_IO+SB_GB - https://git.io/fjIcP
Asu has joined ##openfpga
rohitksingh has quit [Ping timeout: 250 seconds]
rohitksingh has joined ##openfpga
<_whitenotifier-1> [Glasgow] enjoy-digital commented on issue #89: Use SB_GB_IO instead of SB_IO+SB_GB - https://git.io/fjICY
<_whitenotifier-1> [Glasgow] whitequark commented on issue #89: Use SB_GB_IO instead of SB_IO+SB_GB - https://git.io/fjIC3
<_whitenotifier-1> [Glasgow] daveshah1 commented on issue #89: Use SB_GB_IO instead of SB_IO+SB_GB - https://git.io/fjICG
<_whitenotifier-1> [Glasgow] whitequark commented on issue #89: Use SB_GB_IO instead of SB_IO+SB_GB - https://git.io/fjIC8
<_whitenotifier-1> [Glasgow] whitequark commented on issue #89: Use SB_GB_IO instead of SB_IO+SB_GB - https://git.io/fjICB
<_whitenotifier-1> [Glasgow] daveshah1 commented on issue #89: Use SB_GB_IO instead of SB_IO+SB_GB - https://git.io/fjIC1
rohitksingh has quit [Ping timeout: 246 seconds]
<_whitenotifier-1> [GlasgowEmbedded/Glasgow] whitequark pushed 1 commit to master [+0/-0/±1] https://git.io/fjICF
<_whitenotifier-1> [GlasgowEmbedded/Glasgow] whitequark f746966 - cli: suggest valid revisions if --rev fails parsing.
<_whitenotifier-1> [Glasgow] whitequark commented on issue #89: Use SB_GB_IO instead of SB_IO+SB_GB - https://git.io/fjICb
OmniMancer has quit [Quit: Leaving.]
<_whitenotifier-1> [Glasgow] whitequark commented on issue #89: Use SB_GB_IO instead of SB_IO+SB_GB - https://git.io/fjIWG
gsi__ is now known as gsi_
eightdot has joined ##openfpga
<_whitenotifier-1> [GlasgowEmbedded/Glasgow] marcan pushed 1 commit to master [+0/-0/±3] https://git.io/fjI8L
<_whitenotifier-1> [GlasgowEmbedded/Glasgow] marcan cd921fd - revC1: add inline resistors to AUX/SYNC, add testpoints to rear
m4ssi has quit [Remote host closed the connection]
emeb_mac has joined ##openfpga
<bubble_buster> is there anything like https://github.com/riscv/riscv-bitmanip/blob/master/bitmanip-draft.pdf for the J extension?
<bubble_buster> I found the drafts for V, debug, and trace
<sorear> there's no public evidence that J has even started
<vmedea> what would the J extension be ?
<sorear> it's the placeholder letter for "idk stuff for managed languages"
<vmedea> thanks
<sorear> but there's no commercial track record for *anything* actually helping managed languages in a way that's definite enough to standardize
<mithro> Anyone played with https://github.com/wyvernSemi/pcievhost ?
<bubble_buster> arm has done some stuff to speed up javascript pretty well haven't they?
<sorear> not really?
<sorear> they added one new FP to integer conversion
<sorear> they *designed* a Java thing, which turned out to be completely useless
<vmedea> it was also completely secret, which didn't help
rohitksingh has joined ##openfpga
genii has joined ##openfpga
cn04 has joined ##openfpga
<_whitenotifier-1> [whitequark/Yumewatari] whitequark pushed 1 commit to master [+1/-0/±0] https://git.io/fjI4F
<_whitenotifier-1> [whitequark/Yumewatari] whitequark 0981d8c - Add license.
<_whitenotifier-1> [Glasgow] marcan commented on issue #118: Improve ESD immunity - https://git.io/fjI4x
rohitksingh has quit [Ping timeout: 244 seconds]
rohitksingh has joined ##openfpga
cn04_ has joined ##openfpga
<cn04_> daveshah: I heard ecp5-12k has the same die as 25k. Can the extra LUTs past 12k be used by nextpnr/trellis? I saw that there isn’t a separate chipdb for the 12k, so is it basically treated just like it’s a 25k?
<daveshah> Yes
<daveshah> You need to add ` --idcode 0x21111043` to ecppack to change the idcode though
<whitequark> (we don't talk about it)
cn04 has quit [Ping timeout: 256 seconds]
cn04_ has quit [Ping timeout: 256 seconds]
<_whitenotifier-1> [Glasgow] electroniceel commented on issue #118: Improve ESD immunity - https://git.io/fjIBQ
Hellsenberg has joined ##openfpga
<_whitenotifier-1> [Glasgow] electroniceel commented on issue #68: Expose on-board I2C for accessories - https://git.io/fjIRs
<_whitenotifier-1> [Glasgow] electroniceel commented on issue #68: Expose on-board I2C for accessories - https://git.io/fjIR4
<_whitenotifier-1> [Glasgow] whitequark commented on issue #68: Expose on-board I2C for accessories - https://git.io/fjIRw
ayjay_t has quit [Read error: Connection reset by peer]
ayjay_t has joined ##openfpga
<cr1901_modern> https://github.com/smunaut/iua I really could've known this existed 2 months ago lol
<cr1901_modern> ahh well, this is a cool project
<tnt> heh tx :) The FIFO turns out to be the hardest part :p
rohitksingh has quit [Read error: Connection reset by peer]
<tnt> cr1901_modern: did you do some usb work ?
<cr1901_modern> I originally had a saelae clone @24MHz, that died, and I have a USB analyzer on "long term loan" (read between the lines :P)
<cr1901_modern> and now*
<tnt> cr1901_modern: ah, I originally wrote it for https://github.com/tinyfpga/TinyFPGA-Bootloader/pull/21 :)
<_whitenotifier-1> [Glasgow] electroniceel commented on issue #68: Expose on-board I2C for accessories - https://git.io/fjI0l
<tnt> mmm, I'm wondering if tinyusb could be made to support my ice40 usb core ....
<cr1901_modern> mithro and tinyfpga are already porting valentyusb to tinyusb
<tnt> oki. but not the same core :)
<cr1901_modern> But since tinyusb's organization is "per-microcontroller-vendor", I'm not sure how they're handling that the core can be used with an arbitrary CPU
<cr1901_modern> tnt: Anyways, my guess is "probably, but I don't know how to extend tinyusb to be SoC-agnostic for a given USB core"
<cr1901_modern> I would've rather finished this port by using only hobbyist-accessible hardware, so had I know about iua, I would've likely used that next.
<_whitenotifier-1> [Glasgow] whitequark commented on issue #68: Expose on-board I2C for accessories - https://git.io/fjI0E
<_whitenotifier-1> [Glasgow] electroniceel commented on issue #68: Expose on-board I2C for accessories - https://git.io/fjI0u
<cr1901_modern> tnt: >The FIFO turns out to be the hardest part :p
<cr1901_modern> Referring to a certain bug that was fixed today :P?
<_whitenotifier-1> [Glasgow] whitequark commented on issue #68: Expose on-board I2C for accessories - https://git.io/fjI0a
mossmann has quit [Read error: Connection reset by peer]
mossmann has joined ##openfpga
<_whitenotifier-1> [Glasgow] electroniceel commented on issue #68: Expose on-board I2C for accessories - https://git.io/fjI0y
<tnt> cr1901_modern: no, I meant in iua :p
<mithro> iua?
<mithro> Oh, that is tnt's USB core
<tnt> mithro: no, https://github.com/smunaut/iua it's a 2 bit logic analyzer.
<tnt> (granted written so I could debug my usb core, but it's not the core itself)
<mithro> tnt: Ahh
<_whitenotifier-1> [Glasgow] electroniceel opened issue #119: Print IO bank pin mappings on silkscreen - https://git.io/fjI0h
<_whitenotifier-1> [Glasgow] whitequark commented on issue #119: Print IO bank pin mappings on silkscreen - https://git.io/fjIEJ
<cr1901_modern> tnt: So it's fast enough to do real time capture?
<cr1901_modern> iua, that is
<tnt> cr1901_modern: Well, it doesn't have the bandwidth to stream everything for a 100% occupied bus, but for small transactions / enumerations / ... it works just fine.
<cr1901_modern> I assume it relies on the idea that USB has a well defined transition rate, so RLL compression gets good results to send 12 megabits of data down a 115200*(8/9) bit pipe
<cr1901_modern> err (8/10)
<tnt> I think I set the uart to 1Mbits.
<tnt> but mostly it relies on massive idle periods :p
<tnt> and the large buffer of the UP5k.
Asu has quit [Quit: Konversation terminated!]
emeb has joined ##openfpga
Miyu has quit [Read error: Connection reset by peer]
Miyu has joined ##openfpga
Bike has joined ##openfpga
genii has quit [Remote host closed the connection]
futarisIRCcloud has joined ##openfpga