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<SolraBizna>
now the part of the project I've been dreading, where I get to connect ≈200 pins of FPGA
<SolraBizna>
any advice for muddling through the schematic process when most of the pin numbers work out to "whatever pin in bank N is convenient to route"?
<TD-Linux>
don't connect them, start laying out the pcb, then start connecting them
<azonenberg_work>
SolraBizna: Start by making an arbitrary, valid assignment
<TD-Linux>
wish there was back annotation in kicad :(
<azonenberg_work>
But know that it's not going to stay
* SolraBizna
nods
* cpresser
uses a piece of paper for back manual back annotation.
<azonenberg_work>
Once you have the bank-level assignment figured out, then pick a convenient pin and route it to near where you want it to go
<azonenberg_work>
and just swap the pins around
<azonenberg_work>
i dont use drawn wires in kicad for this
<azonenberg_work>
just netname labels
<cpresser>
i use move of labels in the schematic
<azonenberg_work>
so its the work of 5 seconds to move one around and put another one down
<azonenberg_work>
Automating this would be great eventually, but i want it integrated with a constraint solver
<azonenberg_work>
so you can do things like "this is a diffpair and must be placed with its mate"
<azonenberg_work>
or "this pin must be on a clock input"
<SolraBizna>
I have a giant spreadsheet I used to generally assign banks, and I've been planning for nearly all the FPGA connections (in the schematic) to just be "label → pin"
<SolraBizna>
("giant")
<azonenberg_work>
I normally do bank assignment at a much higher level
<azonenberg_work>
not pin level
<azonenberg_work>
First, figure out what voltage level i need
<azonenberg_work>
Group stuff by voltage rail
<azonenberg_work>
Then squish them into banks
<azonenberg_work>
still at an abstract level like "RAM", "Ethernet", etc
<azonenberg_work>
then assign arbitrarily in the schematic
<azonenberg_work>
and do final assignment during routing
<azonenberg_work>
then a secondary manual review when layout is done to make sure all of the pin assignemts are valid
<azonenberg_work>
maybe make a constraint file and compile it to make sure vivado wont choke on it, etc
<SolraBizna>
on this project, things happened to map just about perfectly onto banks
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<SolraBizna>
it'd be madness to try to optimize internal layout by fiddling pin assignments around, right?
<azonenberg_work>
SolraBizna: for timing you mean?
<azonenberg_work>
if you're really pushing performance of the chip maaaybe
<azonenberg_work>
not for general purpose
<SolraBizna>
it'd be for space
<SolraBizna>
(it would be a tiny gain for which the price would be my sanity)
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<whitequark>
xobs: SolraBizna: azonenberg: in glasgow i detect pullups in the jtag-pinout applet that way
<whitequark>
pulse the output real quick and then go into hi-z and measure it after a small period of time
<whitequark>
if it went back it's not floating
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<kervel>
still struggling with fusesoc and icetime, icetime works un the 'icepack -u'd .bin file, but it cannot show the critical path anymore in a symbolic way. only solution for now is run nextpnr by hand.
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<whitequark>
that's expected
<whitequark>
symbols are lost when you pack
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<kervel>
Yes but it would still be nice to be able to use fusesoc during development
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<whitequark>
why does fusesoc use icetime?
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<kervel>
It doesn't, currently. At least that's what I think
<kervel>
I'd like to have timing info while modifying code
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<tnt>
you should really rely on the nextpnr timing analysis rather than the "old" icetime.
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<kervel>
@tnt okay this totally solves it. i didn't know but all timing info i need is in the nextpnr log, how could i miss this.
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<rachit-nigam>
Hi all, I'm looking to build a HLS language on top of LegUp HLS but it seems that the license for the last open source release is pretty restrictive (do not distribute w/ modifications AFAICT). Do people have recommendations for older version of the tool that might be better suited for building free (as in liberty) open source HLS compilers?
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<steve|m>
just got the information that the Gowin GW1NS-2C will be re-released in august with 1.8K instead of 1.3K LUTs, and thus they only have old dev boards available
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