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<emeb>
Interesting experiment in retro - built minimal Z80 system on a up5k w/ just CPU, 2kB RAM, 2kB ROM and 8-bit I/O port. Uses ~44% of FPGA
<emeb>
vs ~23% for equivalent 6502 system.
<tnt>
Not sure if this says anything about Z80 / 6502 ... or whoever wrote the verilog :p
<emeb>
yeah - lots of room for "interpretation"
<emeb>
but similar minimal picorv32 system is ~32%
<emeb>
given z80 vs picorv32 I know which I'd choose.
<tnt>
hehe :)
<tnt>
what fmax does z80 reach ?
<emeb>
16MHz
<emeb>
picorv32 is 24MHz
<tnt>
I actually run a picrorv32 @ 30MHz :)
<emeb>
does nextpnr report that as meeting timing or do you "overclock"?
<tnt>
No, that's what nextpnr reports.
<emeb>
Interesting. Wonder what the difference is.
<emeb>
I'm using the picorv32 that was in your playground repo
<tnt>
emeb: Info: Max frequency for clock 'clk_24m_$glb_clk': 30.49 MHz (PASS at 25.00 MHz)
<tnt>
That's seed 0 with HeAP placer.
<emeb>
Info: Max frequency for clock 'clk_24': 26.14 MHz (PASS at 24.00 MHz)
<emeb>
also w/ heap
<emeb>
and whatever the default seed is
<tnt>
and seed 0 ? Oh, that's a build with BOARD=bitsy also
<emeb>
hmm... don't know about BOARD=
<emeb>
I'm just targeting my own board here.
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<tnt>
emeb: weird ... I mean, I use a different seed than default but other than that it's just the 'usb-test' branch of my repo and a recent nextpnr
<emeb>
Yeah, odd. Well, timing depends on so many things.
<tnt>
it might just be that for your particular IO placement that seed is bad ...
<emeb>
Yeah. I tried a few different ones and the result varied from 23-26MHz.
<tnt>
emeb: are you using the latest code from my repo ? do you have your changes for your board published somewhere ?
<emeb>
tnt: This is a dodgy fork I did of your project a few weeks ago. No idea how far it's deviated from what you've got now.
<emeb>
Probably worth looking more closely. And it's not published anywhere ATM.
<emeb>
But my toolchain was rebuilt last week, so that's not too old.
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<adamgreig>
anyone have any ideas why my standard spi config flash is updating SDO on the clock rising edge, instead of the falling edge like the datasheet suggests? i'm sending it SDI updated on falling edge and it's evidently sampling on the rising edge and decoding the command OK
<tnt>
adamgreig: what model flash ?
<adamgreig>
this is a winbond W25Q80DV
<tnt>
and what makes you believe it does that ?
<Laksen>
How do you know it's updating at rising edges?
<adamgreig>
the saleae decoder gets the correct response EF 40 14
<adamgreig>
my scope decoder gets the same as my spi master, F7 A0 0A, which you get if your sampling is essentially off by one
<adamgreig>
but it sure seems to be changing SDO on the clock rising edge
<tnt>
it sure does
<tnt>
which is ... unexpected
<adamgreig>
yea...
<adamgreig>
i thought it could do spi 0,0 or 1,1 but not this
<Laksen>
What do you think is going on at the second division?
<Laksen>
Just a bump of 0.25 volts out of nowhere? :)
<adamgreig>
the flash chip keeps SDO high-impedance until it receives a valid command
<adamgreig>
my scope only has two channels so you can't see SDI
<adamgreig>
but i'm sending 0x9F (read JEDEC ID)
<adamgreig>
once it receives that it begins driving SDI high to send 0xEF
<adamgreig>
SDO*
<Laksen>
Alright yeah that doesn't seem right
<Laksen>
Do you deassert the chipselect at any time?
<adamgreig>
nope
<adamgreig>
it's asserted, i run the transaction, it gets deasserted
<tnt>
I never used them in mode 3.
<adamgreig>
i get the same behaviour in mode 0 too
<tnt>
ah :/
<adamgreig>
yea :/
<tnt>
adamgreig: did you try to issue a flash reset ?
<adamgreig>
yea
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<emeb>
Lotta ringing on those clk edges - any chance it's misclocking on the ringing?
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<adamgreig>
maybe but i think the ringing is more down to my probing
<adamgreig>
and it's definitely receiving all the correct instructions from me, since it sends the correct thing in response to several different read_id type commands
<adamgreig>
so i think it must be clocking correctly
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<emeb>
Hmm... interesting that if one uses the PLL_2F that it uses up an input IOB
<adamgreig>
if you use the pll at all it uses the input iob, aiui
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<emeb>
yep
<emeb>
Uses both 35 and 37 on the up5k_sg48
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