futarisIRCcloud has quit [Quit: Connection closed for inactivity]
dj_pi has quit [Ping timeout: 264 seconds]
unixb0y has quit [Ping timeout: 244 seconds]
unixb0y has joined ##openfpga
zng_ has joined ##openfpga
zng has quit [Ping timeout: 240 seconds]
dj_pi has joined ##openfpga
dj_pi has quit [Ping timeout: 246 seconds]
zem has quit [Ping timeout: 264 seconds]
zem has joined ##openfpga
Bike has quit [Quit: sleep]
gsi__ has joined ##openfpga
gsi_ has quit [Ping timeout: 250 seconds]
rohitksingh_work has joined ##openfpga
futarisIRCcloud has joined ##openfpga
m4ssi has joined ##openfpga
m4ssi has quit [Ping timeout: 250 seconds]
rohitksingh_work has quit [Read error: Connection reset by peer]
rohitksingh_work has joined ##openfpga
zng_ has quit [Read error: Connection reset by peer]
zng has joined ##openfpga
OmniMancer has joined ##openfpga
futarisIRCcloud has quit [Quit: Connection closed for inactivity]
diamondman has quit [Read error: Connection reset by peer]
diamondman has joined ##openfpga
mmicko has quit [Quit: leaving]
mmicko has joined ##openfpga
Zorix has quit [Ping timeout: 264 seconds]
emeb_mac has quit [Ping timeout: 240 seconds]
Zorix has joined ##openfpga
rohitksingh_wor1 has joined ##openfpga
rohitksingh_work has quit [Ping timeout: 250 seconds]
linzhi-sonia has quit [Remote host closed the connection]
stefanct has quit [Excess Flood]
stefanct has joined ##openfpga
gsi__ is now known as gsi_
futarisIRCcloud has joined ##openfpga
rohitksingh_wor1 has quit [Read error: Connection reset by peer]
stefanct has quit [Read error: Connection timed out]
stefanct has joined ##openfpga
rohitksingh has joined ##openfpga
rohitksingh has quit [Ping timeout: 246 seconds]
gnufan_home has quit [Ping timeout: 250 seconds]
gnufan_home1 has joined ##openfpga
genii has joined ##openfpga
futarisIRCcloud has quit [Quit: Connection closed for inactivity]
<anuejn>
does anyone of you know which algorithm / algorithm class to use for finding the parameters of a pll with multiple outputs?
<tnt>
anuejn: for what device ?
<anuejn>
(Such as the 7 series PLL and MMCM primitives)
<anuejn>
they basically feature a vco which can be controlled by a multiply + divide signal and dividers for all the outputs
<anuejn>
so the main problem is finding the optimal legal vco frequency, so that all the clocks have minimal error
<anuejn>
but how to do that?
<tnt>
exhaustive search
<tnt>
the vco has a limited range, so each output will only have so many divider that can possibly work.
<anuejn>
ok thanks
<anuejn>
you dont think, there is something better?
<tnt>
Not that would be worth implementing. It's not going to find a better solution and the time to do the full search is going to be imperceptible ...
<tnt>
Technically it's an overdetermined system of equation that you're trying to minize with integer solutions ... I'm sure there are math libraries that could do that, but that seems _way_ overkill.