<sorear>
I don’t want to see a “VHDL frontend”. We need a unified frontend so that libraries work can be shared …
<mithro>
sorear: Get hacking then....
<sxpert>
sorear: I meant, something at the same level as "read_verilog"
<cr1901_modern>
I still say NVC -> RTLIL is prob the best bet; at least the parser part is done.
<daveshah>
RTLIL, or any other sensible IL, isn't enough
<daveshah>
You also need some method of callbacks to the frontend to re elaborate with different parameters
<cr1901_modern>
daveshah: NVC is a VHDL simulator, so it does the elaboration during simulation
<cr1901_modern>
the idea is to run as little of the simulation as required to do all the elaboration
<daveshah>
That's not the problem I raised
<daveshah>
The problem is that a standard interface is needed to deal with a Verilog module instantiating a VHDL module with parameters
<daveshah>
This will require reelaboration, which the hierarchy command in Yosys or equivalent needs to invoke
<cr1901_modern>
mmm... someone else can handle that part :P. Only interested in VHDL to the extent that j-core processor is written in it
<cr1901_modern>
(so NVC -> RTLIL would allow a fully free flow to make a j-core SoC, but wouldn't allow mixing verilog and vhdl)
<cr1901_modern>
tbh, that it's written in vhdl is mainly why I haven't personally contributed to it- I like SuperH :(
<daveshah>
How much of the non-Verilog-equivalent feature set does it use?
<cr1901_modern>
Lots
<cr1901_modern>
This is from talking to the "Jeff" in "J"-core the one time I've seen him in IRC.
<cr1901_modern>
In fact, the NVC port is his idea- j-core already works w/ that simulator
<daveshah>
There's also ghdlsynth
<daveshah>
But extending that means working in Ada :/
<cr1901_modern>
NVC is C
<cr1901_modern>
so "just" make it emit something yosys understands and call it a day
<daveshah>
The advantage with ghdlsynth is that the Yosys integration is already in place
<daveshah>
It just needs support for more features added
<cr1901_modern>
hmmm
<sorear>
can we get egg to do it then
<cr1901_modern>
NVC _feels_ like more work in the long run has already been done for me. Guess it's a balance of "how difficult is it to add the required VHDL features to ghdlsynth" versus "how difficult is it to add yosys integration to NVC"?
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<_whitenotifier>
[Boneless-CPU] zignig synchronize pull request #3: Text Assembler for boneless (WIP) - https://git.io/fhxmz
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