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<_whitenotifier> [Boneless-CPU] zignig synchronize pull request #3: Text Assembler for boneless (WIP) - https://git.io/fhxmz
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<_whitenotifier> [Boneless-CPU] zignig synchronize pull request #3: Text Assembler for boneless (WIP) - https://git.io/fhxmz
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<_whitenotifier> [Boneless-CPU] zignig synchronize pull request #3: Text Assembler for boneless (WIP) - https://git.io/fhxmz
<_whitenotifier> [Boneless-CPU] zignig synchronize pull request #3: Text Assembler for boneless (WIP) - https://git.io/fhxmz
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<Richard_Simmons> I'm looking at gddr5 stuff, and it seems a lot like it wants to be used by anything.. it can clock low, it doesn't need trace length matching, and just does a lot to not care about PCB or speed of the device, but does sound like it asks for a lot of features on a memory controller to support that. Makes me wonder about gddr5 on ecp5s. >.>
<sorear> how many pins does it need, what's the minimum speed, and how fussy is the timing at that minimum speed?
<Richard_Simmons> I think it was 61 pins, 32bit databus but also has features to do 16bit, and this specifically states "200Mb/s " as a use-case example, not sure how low it can actually go. https://www.micron.com/~/media/documents/products/technical-note/dram/tned01_gddr5_sgram_introduction.pdf
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<Richard_Simmons> really not sure how fussy timings are. Couple documents to various devices and don't see anything that spells it out so far, but I do know how to decode timing-straps in amd atombios's that have specs for 300mhz speeds.
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<Miyu> could I perhaps get a current copy of the 25k bba file again from someone, for validating my import tool? Thanks :)
<Miyu> thank you very much :)
<shapr> sxpert: thanks for those EMC links, good rabbit hole to explore
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<_whitenotifier> [Boneless-CPU] zignig synchronize pull request #3: Text Assembler for boneless (WIP) - https://git.io/fhxmz