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<_whitenotifier> [Boneless-CPU] zignig synchronize pull request #3: Text Assembler for boneless (WIP) - https://git.io/fhxmz
<azonenberg> Welp, FREESAMPLE is getting closer to done every day
<azonenberg> Up to 464 components and down to 15 ERC errors
<azonenberg> several of which are probably due to the fact that the +2.5 and +1.8V power supplies don't yet exist
<azonenberg> and the FPGA/MCU boot and reset straps haven't been installed
<hl> nice switch project. are multi-port phy chips hard to find?
<azonenberg> hl: this is the sampling oscilloscope, LATENTRED is the switch
<azonenberg> I will be using it ON the switch, in order to verify backplane signal integrity :)
<hl> ah yeah, I was literally just reading the github about LATENTRED
<azonenberg> But it's not the switch itself
<azonenberg> They do both use the same FPGA+MCU module (INTEGRALSTICK) though
<azonenberg> the fpga is too small to fit the switch fabric in, but it's the perfect size for an I/O expander
<azonenberg> and the kintex i'm using on latentred doesn't have enough GPIOs in the package I selected, so...
<azonenberg> the full architecture calls for the management CLI on the integralstick stm32, i/o expansion and glue on the integralstick artix, and the switch fabric on the brain board kintex
<hl> talking of LVDS retimers, a while ago I tried to find discrete LVDS-serial-to-parallel chips (basically like an FPGA transceiver but external)... do they really not exist? :/
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<azonenberg> They do, but not faster than a few hundred Mbps
<hl> yeah. annoying
<azonenberg> Or with really narrow bus widths
<hl> you'd figure there'd be a market
<azonenberg> The TLK10232 that i'm abusing as a clock recovery circuit is 4 lanes 8b10b @ 3.125 Gbps -> 1 lane 64b66b @ 10.3125 Gbps
<hl> you can get PCIe Gen1 x1 PHY chips, sometimes I wonder if you could use those for non-PCIe things
<azonenberg> aka XAUI to SFI (two lanes of each in one chip)
<hl> I also know SATA PHY chips used to exist looong ago but have long since ceased to be available, not surprisingly
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<_whitenotifier> [Boneless-CPU] zignig synchronize pull request #3: Text Assembler for boneless (WIP) - https://git.io/fhxmz
<azonenberg> Lol
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<hl> in other news, I was thinking whether one could make a PCIe debugger with an ECP-5G; one upstream lane, one downstream lane, acting as a switch chip, with a 10GBASE-T output spamming all TLPs as Ethernet frames
<azonenberg> hl: Have you tried to buy 10Gbase-T PHYs?
<hl> unfortunately, XGMII PHYs don't seem readily available anymore (without NDA at least), since everyone's moved to XAUI
<azonenberg> last time i checked they're unobtainium
<hl> figures :/
<azonenberg> This is why i wired my house with CAT5e instead of CAT6
<azonenberg> 10Gbase-T is dead to me
<azonenberg> there's plenty of multimode fiber, but i won't be using *copper* past 1 Gbps :p
<hl> but anyway, ECP5-5G tops out at 4 tx/rx transceiver pairs, right? So one for PCIe uplink, one for PCIe downlink, leaving only two for XAUI but you need four... doesn't work
<hl> oh, you're quite right
<hl> 10GBASE-T is crap, e.g. from a power consumption standpoint
<azonenberg> hl: RXAUI is a thing, 2 lanes @ 5 Gbps -> 1 lane @ 10 Gbps, but it's a... broadcom? proprietary standard
<azonenberg> (also latency, all the FEC slows it down vs just 64/66 coding raw layer 2 frames)
<hl> oh no, not broadcom
<azonenberg> broadcom, marvell, and vitesse are on my blacklist of companies that i refuse to do business with
<azonenberg> because they've brushed me off when i tried to get parts/docs
<hl> yeah broadcom is fucking asinine
<azonenberg> As a result, they will never get a design win from me for the rest of my life
<azonenberg> *especially* high volume commercial products
<hl> apparently the datasheets they do hand out are literally watermarked with the name of the company they gave them to, and are password-protected PDFs. wtf
<azonenberg> qualcomm would be on the list, except i know better than to even attempt to get stuff from them
<azonenberg> so they never hit the threshold of refusing to do business with me :p
<hl> since you're interested in switching I'm sure you'll share my irritation of the lack of documentation available for e.g. Trident II, etc.
<azonenberg> Good news is, once prjxray gets the 7 series GTX's working
<azonenberg> you'll be able to do the project you want on a reasonable budget using open tools
<hl> yeah, that will be absolutely fantastic
<hl> closed tools are a dealbreaker to me ofc
<azonenberg> an xc7k70t or 160t has a hard PCIe block and 4 or 8, depending on packages, 10G transceivers
<hl> and I hear the closed tools are pretty horrid anyway
<azonenberg> Well, unfortunately my needs exceed the performance capabilities of f/oss friendly chips
<azonenberg> So i tolerate vivado and hope prjxray catches up enough i can switch
<hl> aah, makes sense
<azonenberg> latentred will use a 7k160t and use every GTX
<azonenberg> latentorange is going to be an ultrascale or ultrascale+ part :p
<azonenberg> (10G access ports and 40G uplinks)
<azonenberg> there simply are not any open/reversed parts with that kind of performance
<hl> yeah.
<azonenberg> and not being a stallman-level zealot i'm not going to refuse to do a project just b/c no free tools work on the part
<azonenberg> i use free tools in preferenec to proprietary ones if they exist, and can match the performance/capabilities
<azonenberg> but first and foremost i need to get the job done
<hl> yeah, I certainly don't begrudge others for using ##closedfpga - just a personal preference
<azonenberg> freesample miiight fit in an ecp5-5g but i already have an existing xilinx module (integralstick) that i was going to use as the brain
<azonenberg> that being said, i am all for making a lattice based pin-compatible integralstick replacement
<hl> I was really happy to see the whitebox switch movement ("provide your own OS" etc.) -- but we seem to be going through the same deal we had with GPU vendors 10 years ago with Linux -- not seeming to understand that it doesn't help them to sell product to refuse to tell people how to actually program their products
<azonenberg> (or just using nextpnr+prjxray on the artix)
<azonenberg> hl: yeah, i figured opening the fpga was more likely to happen than opening the switch asic
<azonenberg> plus, if i cant get docs for the switch asic it's useless to me
<azonenberg> Or, if i can't buy one of them
<azonenberg> digikey doesnt even stock most of the parts in question
<azonenberg> heck, i can't even get pricing
<hl> azonenberg: yeah, opening the switch ASIC won't happen... I don't even mean opening it, just providing the damned register manual...
<hl> azonenberg: you could look into mlxsw? _they actually mainlined their driver_
<hl> so their driver is FOSS, which is something
<azonenberg> well, i wanted the ability to do fun things in the datapath
<hl> certainly makes me wonder if their culture is at least one order of magnitude less fucked up than broadcom
<azonenberg> like, layer 1 packet sniffing
<hl> ah
<azonenberg> (including preamble and FCS, with nanosecond-level timing)
<azonenberg> shoved inside udp frames and sent out a span port using a special protocol
<azonenberg> or signal processing, or even just reusing the board to be something other than a switch
<azonenberg> i have some plans already to use the latentorange fpga board to do DSP on a bunch of fast ADC/DAC boards hanging off 40GbE links
<azonenberg> given the O(1) cost of making an 8+ layer board, it makes sense to do as few as possible and repurpose them as needed
<hl> yeah
<hl> so really I'm very new to EE after not really getting it for a long time, but I finally feel like I can figure it out... have some basic oshpark boards I'm toying with just to get started for now
<hl> the other day I was pondering PC-attached oscilloscope construction (why have these standalone oscilloscopes when I have a much more powerful PC with a bigger display?) -- not hard to send downsampled data for screen rendering, but full-rate data streaming opens up a ton of interconnect difficulties
<azonenberg> So, i am planning to make one
<hl> (cc JSharp )
<azonenberg> My proposed design is a match for my new lecroy in specs
<azonenberg> 4 channels @ 10 Gsps 8 bit
<hl> nice... what's the interconnect?
<azonenberg> Tentative plan is 10GbE from each channel board to the root FPGA
<azonenberg> Then 40GbE from the root to the host PC
<hl> ah, sounds good
<azonenberg> each channel will have a small fpga that's basically an adc controller dma'ing to a dac
<azonenberg> then the bigger FPGA will be in charge of merging all the data and sending to the host
<azonenberg> The front panel will be four SMAs and one QSFP+
<azonenberg> headless 1U system
<hl> ah, right - I was also thinking of using SFPs, because another advantage there is you can get electrical isolation via fibre
<azonenberg> It won't be able to stream full rate, you'll have to capture a waveform to the onboard DDR3 then send back to the host
<hl> don't really want to accidentially nuke my PC
<azonenberg> full rate off the ADCs will be 320 Gbps
<hl> yeah
<azonenberg> So you'll have to be capturing 1/8 of the time and sending data the rest of the time, although you can obviously capture at full rate for a short time
<azonenberg> i already started prototyping an OpenGL based clientside rendering application
<hl> cool
<azonenberg> (actually drawing hundreds of kWFM/s in realtime is nontrivial)
<azonenberg> with a nice digital phosphor style compositor and everything
<azonenberg> plan was to develop the UI using my lecroy as the back end, and just reduced network performance since my old scope is 100M and the new is 1G ethernet
<azonenberg> then when the hardware was ready, start using my scope
<hl> though really, 95% of applications will probably be satisfied with just enough resolution to the data for graphical rendering - at which point I was thinking I may as well just use USB3, I suspect
<azonenberg> But my shorter term test equipment project is freesample
<azonenberg> because i cannot afford a 10 GHz realtime scope
<azonenberg> and doubt i will be able to any time soon
<hl> hah, yeah, what are those, $3.2M?
<azonenberg> eh, i dont think quite that much
<hl> ah. I know one 10GHz scope cost that much, but maybe that had special features
<azonenberg> The lowest end lecroy labmaster is 4 channels @ 20 GHz b/w and 80 Gsps
<azonenberg> and the website says they start at $114.3K
<hl> oh, sorry, my memory failed me
<hl> I was thinking of a 110GHz scope
<hl> ha.
<azonenberg> ah ok that makes a lot mroe sense for the price tag
<azonenberg> yeah 10 GHz scopes are probably in the $30-60K ballpark
<azonenberg> But mine will be $3K range :p
<hl> er, $1.3M not $3.2M. wtf is wrong with my memory
<azonenberg> maybe less
<azonenberg> My digikey cart is $750 right now, plus the FPGA module brings it up to about $1K in components
<azonenberg> then i dont know how much the ~8 layer impedance controlled PCB with ViP will cost, but i'm ballparking 1.5K in low volume
<hl> I sort of gather that the test equipment market is a bit of a racket... I've heard once in a while, a company will start up making much cheaper equipment, and they usually get bought by the big boys to put a stop to that
<azonenberg> yeah well my design will be open source and i'm not selling out to anyone :p
<azonenberg> so we'll let them have fun with it
<hl> yep
<azonenberg> to be fair mine is a sampling scope, not a realtime
<azonenberg> you're looking at probably 15 minutes for a single eye pattern
<hl> obviously the emergence of cheapr chinese equipment, and FOSS stuff is putting a stop to this gradually
<azonenberg> (with 30K averages)
<hl> aah
<JSharp> *looks in* cool! I'll read the whole discussion once I'm home from work
<sorear> hl: if you dig through the slide decks about technology development for high-rate (28 Gb/s and above) SERDES, what everyone seems to do is 28+ Gsps ADC followed by equalization and decision in logic
<sxpert> azonenberg: and, in a couple years or so, we could have libresilicon switch asics out of the fpga code
<hl> interesting
<sorear> yet somehow, high-speed SERDES are far closer to being a commodity than the ADCs that are used as a subunit thereof
<hl> so you basically use a high-speed ADC as a transceiver? hmm
<hl> oh, well, that's just usual market silliness -- not all that surprising ;)
<sorear> >1 Gsps continous-operation ADCs are … close to oscilloscope prices
<sorear> iirc the current milestone is 56 Gbaud (i.e. 28 GHz cutoff) PAM4 (112 Gb/s) with uncorrected BER 10^-4
<sorear> blanking on the name of the document that covers this
<TD-Linux> aren't 28Gb/s+ serdes also like oscilloscope prices?
<hl> that's a horrid BER
<sorear> the biggest ultrascale+ is less than half the price of the lecroy upthread and I think several of the smaller/cheaper ones also have GTZ
<sorear> but azonenberg is the one with the xilinx product table memorized
<sorear> hl: it's going to be interesting to watch what PCIe gen 6 does about coding delay, for sure
<hl> yeah
<hl> have they confirmed that Gen5 will not need connector changes/anything peculiar yet?
<hl> but I think it was kinda borderline, I recall wondering if they would be able to keep it normal for Gen5
<hl> so Gen6 will probably get weird
<sorear> I have no idea
<sorear> mostly I'm wondering if photonics are going to be practically relevant before or after fusion power
<hl> well
<hl> apparently vendors really wanted to use Intel's silicon photonics TB, but they wanted to charge an absurd amount on patent royalties?
<hl> for the lenses, IIRC
<sorear> huh. how long ago was that? do any other vendors have viable products? what does it look like in throughput / latency / fJ per bit?
<hl> i honestly have no idea
<hl> your best bet might be patent searches?
<sorear> mm
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<azonenberg> Back
<azonenberg> So, 28G/32 is about the limit of what i see with curent generation NRZ SERDES
<azonenberg> Most of the higher speed stuff is PAM4, like 56/112G
<hl> yeah, 25-28G seems like the current limit for non-PAM SERDES
<azonenberg> PAM4 does generally have awful BERs though, so pretty much anything using one of those serdes is going to have to use FEC which adds latency
<hl> eesh
<azonenberg> Does anybody know how many bits of resolution these new-gen serdes ADCs have?
<azonenberg> I havent seen a straight answer but am very curious
<azonenberg> Or what kind of architecture they're using? assuming probably some kind of folding interpolating
<azonenberg> For a point of data re using adcs as serdes, even 1000base-T normally does this
<hl> interesting
<azonenberg> I did it at 100base-TX for TRAGICLASER too
<azonenberg> in a way
<azonenberg> i used two LVDS inputs and 3 resistors to make a 1.5 bit flash ADC
<hl> Do you like naming things like NSA projects? ;)
<azonenberg> running at 500 Msps, then did CDR based off that
<azonenberg> I suck at inventing names for things
<azonenberg> name = "AWFULPROJECTNAME"
<azonenberg> while(!soundsGood(name))
<azonenberg> name = randomWord() + randomWord()
<azonenberg> In a few cases i actually pick or somewhat guide the process
<hl> fairly sure the NSA uses that code too, heh
<azonenberg> for example FREESAMPLE is a F/OSS sampling oscilloscope
<azonenberg> the name just kinda made itself
<azonenberg> STARSHIPRAIDER is {bus, pirate} + future
<hl> reminds me of the random words used as cheat codes in various games
<azonenberg> i.e. mode of transportation + thief
<azonenberg> then LATENT* originally was LATENTPACKET, which remains the overall project name
<azonenberg> but I decided to go with a "family name" for LATENTRED, LATENTORANGE, etc
<azonenberg> in the same vein as NSA's QUANTUMINSERT, QUANTUMTHEORY...
<azonenberg> sorear: re high speed ADCs not being commodity, my guess is that the ADCs used in SERDES are very few bits and have awful distortion characteristics
<azonenberg> as they only care about the frequency band around the baud rate
<azonenberg> The fastest ADC on digikey is the HMCAD5831 which is a *3 bit* 26 Gsps converter, and it's also EOL with a last time buy date 2 months ago
<azonenberg> not sure why it's even still on the site
<azonenberg> 4.2 watts power consumption, lol
<sorear> I have no idea about the architecture or how to find out anything
<azonenberg> This one is a flash, they say
<sorear> the logical endpoint of the electronics industry is full monolithic integration of everything into consumer products and the end of public documentation for anything
<azonenberg> The next fastest adc is the LM97600 which is 7.6 bits with a serial LVDS interface
<azonenberg> and is only $311
<azonenberg> 5 Gsps
<azonenberg> it would make a very nice and affordable scope if you don't mind the rather low bit depth
<azonenberg> it's four interleaved 1.25 Gsps converters in one package, with internal interleaving
<azonenberg> it's a rather bizarre architecture though, the output data *varies in size*
<azonenberg> sometimes 7 bits sometimes 8
<azonenberg> i have no idea what the internal design could be like to do that :p
<sorear> mm, robbed-bit signalling
<azonenberg> THen you start to see more "fun" parts like the ADC08DJ3200AAV
<azonenberg> full 8 bits, 2 lanes @ 3.2 Gsps or 1 @ 6.4 Gsps
<azonenberg> just over $1K on digikey, with a 16-lane JESD204 interface
<azonenberg> (although if you have 10G SERDES you can up the bit rate and not use all the lanes)
<azonenberg> looks like you can run at 2.5/5 Gsps on 4 lanes or up to 3.2 Gsps with 8 lanes
<azonenberg> the 16-lane mode is just catering to chips with slower serdes i guess
<azonenberg> That might not be a bad part to use in a DSO, two of them interleaved gives you 12 Gsps for $2K
<azonenberg> if you can live with 10 Gsps, you only need 8 transceivers for the interleaved pair
<azonenberg> meaning a 4-channel scope would need 32 transceivers, or a couple of smaller FPGAs
<azonenberg> the cool thing about that part for a DSO is that it claims full power bandwidth out to 10 GHz
<azonenberg> meaning you could make the default mode of the scope be 1 GHz / 10 Gsps realtime operation, but also switch into an equivalent time mode with 10 GHz bandwidth and super fine sample steps
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<sxpert> azonenberg: nvidia eating up mellanox for $6.9B
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<shapr> nvidiband
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<plaes> o_O
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<azonenberg> interesting
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