<
emeb>
tnt: well, my wishbone master is definitely locking up when I try to access the SPI IP core - like it's not getting an ACK back from it.
<
emeb>
so should probably try building the design with icecube and see if that works.
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<
tnt>
emeb_mac: mm, seems like I get ACKs here (AFAICT so far at least)
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emeb_mac>
tnt: ah, that's good to know. I must be doing something wrong in my wb master.
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tnt>
Well, I haven't gotten the IP to do anything yet so ...
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tnt>
were you trying read or writes ? is your code somewhere ?
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emeb_mac>
tnt: I was doing reads - trying to see if I got non-zero results for anything.
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emeb_mac>
I haven't checked in the code into github yet.
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emeb_mac>
I can see that the RDY output of the master is high to start, then drops when I try to read and never asserts again
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emeb_mac>
so it seems that I'm not getting an ACK back to restore it.
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emeb_mac>
gotta go - bbml
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tnt>
Mmm ... it seems to not acknowledge the reads indeed, but I have the same issue with arachne-pnr :/
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tnt>
Oh wait ... no I swapped CS and WE :/
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tnt>
yeah, works better when they're the right way around. I can read/write registers.
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tnt>
So far I didn't manage to make it do anything really though ...
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tnt>
CLK and data signals look good, just CS is missing :/
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tnt>
Mmm, it like MCSNOx is swapped with MCSNOEx ...
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tnt>
daveshah: do you think there could be an error in the chipdb ?
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daveshah>
Could be, would be worth comparing against icecube
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daveshah>
This has been very lightly used
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daveshah>
but it doesn't use CS....
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tnt>
yeah that's what I was about to say :)
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tnt>
How can I check the output of icecube ?
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daveshah>
You'll need to connect the relevant signals to top level pins
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daveshah>
and then see where the wires driving those pins come from in icebox_vlog
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daveshah>
Although it might be easiest just to see if the design works in icecube or not
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tnt>
err not really, it doesn't build in icecube atm :p
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tnt>
(the full design I mean ... with the softcore and everything)
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tnt>
Mmm ... output from icebox_vlog seems to match :/
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daveshah>
Maybe double check the icebox_explain output too
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tnt>
mmm ... this is so confusing :/
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tnt>
SPICSR might be inverted , so you need to set them all to 1 and set to 0 the one CS you wish to address.
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daveshah>
The Radiant sim models include unencrypted RTL for both the SPI and I2C blocks
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daveshah>
If you really want to look into it
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daveshah>
(the icecube ones are encrypted BTW)
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tnt>
daveshah: Oh nice
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tnt>
Ok, yeah so indeed the SPICSR register expects to be set to 0xff when idle, it's an exact mirror of what's going to be put on the pins.
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tnt>
Also the MCSH bit, if not set, if you don't set a new data in time ... it will just repeat the previous byte ... that's just weird.
<
emeb_mac>
hmm. still can't get mine to ACK.
<
tnt>
emeb_mac: maybe reads don't work until you actually write values that make sens in the registers.
<
tnt>
like the 'enable' bit and a correct baudrate.
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emeb_mac>
tnt: interesting idea - will give it a try
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tnt>
\o/ I was able to read the flash ID.
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