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<rektide_>
why was i not in this channel? hello. there was a project that went by a couple weeks ago on twitter, about an open source RAM controller of some kind? if anyone has names or links to things that might fit this description & be under semi-recent development, i'd love to find it again
<rektide_>
i'm so interested in how we get from synthesizing logic to being able to build the rest of the chip too- the interfaces (not my area therefore so so curious). i don't know if this RAM related project did that or was just a logical controller, but i'd love to better understand what they were going for
<rektide_>
yeah! ty. ok this helps interface with ASIC sram blocks
<whitequark>
it's more that it outputs asic sram blocks
<whitequark>
>OpenRAM is an open-source Python framework to create the layout, netlists, timing and power models, placement and routing models, and other views necessary to use SRAMs in ASIC design. OpenRAM supports integration in both commercial and open-source flows with both predictive and fabricable technologies.
<rektide_>
i was still thinking from that description it meant talking to existing resources, rather than defining those resources. i confess i'm a chip-making n00b, so didn't get that ASICs don't already have blocks or that you might want to make more.
<whitequark>
an ASIC is a blank slate
<whitequark>
in the most general form
<whitequark>
if you have a multi project wafer you can very well be restricted in many ways
<whitequark>
i think usually you have to use the pad ring provided by the shuttle service and usually you want to use the fab's cell library and memory macros as well
<rektide_>
would that cell library often include transcievers of various sorts? is there any work like openram but for transcievers where we can, for example, define our own usb3 or pcie interfaces, rather than relying on cell? that is the sort of thing one might see in a cell library, yeah?
<whitequark>
hahahahahaha no
<rektide_>
that's all chip to chip to dedicated PHY?
<whitequark>
we're multiple major advances in FOSS silicon behind transceivers
<rektide_>
can asics fill that role?
<whitequark>
the cell library is just stuff like flip-flops and logic gates
<rektide_>
oh, ain't kidding about "cells"
<rektide_>
i realize full well it's dreaming but i spent like 8 hours looking for a monitor/recorder for my camera, & once again was hit with wanting to know how & where transcievers are made & how some day we might be able to make chips with neat transcievers on them
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<rektide>
i get this tho: "we're multiple major advances in FOSS silicon behind transceivers"
<sorear>
my understanding is that the condensed matter physics needed to calculate transistor transfer parameters from first principles doesn't exist
<sorear>
so if you want to make a *working* transciever you need to do chips for just process characterization, which is a substantial investment of money, time, and NDAs
<sorear>
a 112G PAM4 SERDES is going to have different challenges from a 72b-wide DDR4 interface
<sorear>
also, welcome
<sorear>
not sure where the qflow etc discussion happens, it's definitely not here and it's only occasionally #yosys
<rektide>
đź‘Ť! sorry for being pretty off topic. #yosys is a good recommendation, much appreciated. i get that it's hard & requires a lot of process characterization.
<sorear>
this channel is pretty off-topic friendly
<sorear>
don't feel like you're imposing as long as it's tangentially related to either EDA tools or the people here
<sorear>
https://forums.efabless.com/ doesn't have anything obviously relevant to opencircuitdesign.com being down; i'd check the qflow mailing list but it's hosted on the same server as the qflow site
<sorear>
qflow/opencircuitdesign/efabless is, as far as I know, the leading edge of non-secret IC design
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<emeb>
Gads - just updated my icestorm/yosys/nextpnr installs and the compile times are way quicker than before. What happened?
<daveshah>
I honestly don't know - the HeAP placer gives a good speedup, but isn't default for iCE40 yet...
<emeb>
I mis-spoke. I mean the build times for the tools themselves.
<emeb>
icestorm and yosys in particular took significantly less time to build.
<daveshah>
Think there've been a couple of icestorm PRs related to build times
<daveshah>
Not sure about Yosys
<tnt>
emeb: are you sure you didn't have previous build results already present ?
<emeb>
tnt: I did a make clean before each.
<emeb>
perhaps that doesn't remove everything tho?
<tnt>
I'm not sure if make clean erases the ice40 db bba
<tnt>
For me, in yosys ABC is what takes a while and it's not often updated so even a git pull doesn't rebuild it often AFAICT. And for the ice40 it's the databases.
<emeb>
Same.
<emeb>
Now to go see if I can plop down an RGB driver in u4k...
<tnt>
didn't you test that already ?
<tnt>
I might be confused.
<emeb>
Support for that wasn't pulled into mainline until this morning.
<tnt>
yeah, nm, I got you confused with the guy that implemented it :p
<emeb>
corecode did it last week but clifford didn't accept the PR until now.
<tnt>
I'm getting old
<emeb>
lol
* emeb
won't discuss how old he is
<Ultrasauce>
what are you working on these days emeb
<emeb>
Ultrasauce: "working" is a rather broad term... ;)
<emeb>
but the current projects on the bench are some u4k and up5k based retrocomputing boards.