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* ZirconiumX
makes important Yosys bugfix
* ZirconiumX
quintuples the cell count of PicoSoC
<
ZirconiumX>
For Cyclone V, don't worry
<
ZirconiumX>
The people with sane EDA flows are fine
<
ZirconiumX>
Where sane == "doesn't map a BRAM cell that does not exist on the target architecture"
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<
ZirconiumX>
Yay, I broke Quartus
<
ZirconiumX>
By feeding it with a VQM from Yosys
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<
tnt>
daveshah: do you see anyway to make a clock mux in an ice40 ?
<
tnt>
(transitions doesn't need to be any good, all relevant circuits would be forced in reset while going from clkA to clkB)
<
daveshah>
For that purpose a LUT would probably be fine
<
daveshah>
As a single input would only be changing (the clock) I doubt there'd be glitches
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