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<tnt>
wrt to HFOSC. So what it looks to me is that trim[9] does ... nothing. Then you have two segments one of 5 bits, one of 4 bits, each controlling a different way of tuning the frequency. One coarse (5b) and one fine (4b). But their tuning range overlaps a bit (i.e. the LSB of the 'coarse' range is smaller than the MSB of the 'fine' range).
<whitequark>
that seems reasonable, actually
<tnt>
yup, doesn't seem implausible. The coarse also seem strictly monotonic (on the super representative sample size of 2). The fine one is not, but not far off ... (the lsb is sometime off).
<daveshah>
I've checked and I'm pretty sure the MSB is wired correctly in icebox, so not sure what it is trying to do
<daveshah>
Perhaps some other kind of adjustment
<tnt>
daveshah: yeah, it doesn't seem to affect the frequency at all actually.
<tnt>
Maybe it tweaks the jitter or duty cycle. I'm not setup to measure that ATM.
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<cr1901_modern>
https://github.com/pgate1/SNES_on_FPGA It's a SNES. On an FPGA. Most interesting thing (besides that a FOSS version exists now) is that it's written in a language I've never heard of
<cr1901_modern>
SFL: Structured Function description Language
<whitequark>
it;s some japanese research project
<whitequark>
>The latest version of PARTHENON, version 2.3, which runs on SPARCstation or HP/Apollo, is now on sale. PARTHENON/CQ, a version customized for use by MS-DOS users, is also available. The CQ version is functionally equivalent to the workstation version, except that it imposes a limit of about 2,500 gates on the size of circuits that can be handled.
<cr1901_modern>
Yea I saw that. I asked how I'm supposed to compile it, waiting to hear back. Not that I have Quartus installed right now in the first place.
<cr1901_modern>
I HOPE that is horribly out of date
<whitequark>
>In the course of processing by auto.bat, as shown in Section 7.3, the 'flat' command was used several times. It was necessary to flatten the hierarchical structure of the design to get around the problems arising from certain restrictions in the MS-DOS file system. Since the PARTHENON workstation version does not suffer from such restrictions, the design hierarchy can be retained up to the final
<whitequark>
netlist, and the hierarchical structure can be changed freely.
<whitequark>
this is cursed
<whitequark>
i'm not sure what i think about the language itself
<whitequark>
it has some interesting ideas, certainly
<cr1901_modern>
I'm not about to drop omigen/nmigen for it, but it looks pretty readable. I HOPE there's a FOSS compiler. I would be curious to port this design to Xilinx (I don't have any ice40 boards w/ VGA and Idk if it would fit).
<cr1901_modern>
Anyways, I found references to a "sfl2vl" binary, a project separate from parthenon. But no actual luck finding a converter. My guess at this stage is that providing the source is a courtesy, but it is actually fairly difficult to compile without having a licensed tool :(
<cr1901_modern>
no actual luck finding the compiler source*
<Hoernchen>
i can't see anything open source related to that