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<azonenberg> cr1901_modern: yes, afaik gp5 is as documented as gp4
<azonenberg> it's just that i never had the time to add a backend for my tools
<azonenberg> especially the new blocks like the async state machine, which would be somewhat nontrivial to implement inference for in HDL
<azonenberg> the other issue is that the newer greenpaks have a lot more resource sharing going on, where you might have a block that's either a DFF or a LUT
<azonenberg> but can't be both at once
<azonenberg> my rather simplistic techmapping wasnt smart enough to handle that
<whitequark> nextpnr should be able to handle that very well
<whitequark> and it's under ISC so you should be able to just contribute to it
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<azonenberg> whitequark: rewriting the toolchain to use my existing yosys synthesis and techmapping followed by nextpnr has been a planned project for a long time
<azonenberg> i've been too busy to touch it
<azonenberg> I wanted to try nextpnr for coolrunner too
<whitequark> nice
<azonenberg> My problem for the last few years has been too many things going on and not enough minions to help me with them
<azonenberg> I'm slowly working on trying to fix that, in the middle of training up a friend to be an assembly tech for me so i don't have to build boards by hand anymore
<azonenberg> yes i could outsource it, but for one-offs most PCBA shops just pay a tech to do the work anyway
<whitequark> minions
<azonenberg> The house project is winding down so that's one less thing on my plate, we're moved in now but still have a bunch of unpacking to do as well as some trim and fiber cable installation that i've been putting off
<azonenberg> whitequark: would you prefer "henchmen"? :p
<azonenberg> that implies more of a subterranean volcano lair though
<whitequark> people usually call them "interns"
<whitequark> or "assistants" perhaps.
<azonenberg> Lol
<azonenberg> That doesn't have the same mad scientist sound to it
<whitequark> idk, "minion" sounds sort of degrading to me
<whitequark> doesn't really matter i guess
<azonenberg> In all seriousness it's a disabled friend interested in learning more about tech stuff who lives alone and recently lost her job
<azonenberg> i figure if i can pay her 25 USD/hr or something to build boards for me here and there it'll give her some extra cash and keep her from being bored around the house all day
<whitequark> 25 USD/hr for PCBA isn't bad
<azonenberg> and it's better than she was getting delivering pizzas
<azonenberg> it wouldn't be too many hours a week of course, but that's time i can spend on more interesting stuff
<azonenberg> so seems like a good deal for all parties
<azonenberg> i'm not expecting an expert engineer, just somebody who can run a stencil and tweezer parts, watch the oven, then hand solder some PTH connectors
<azonenberg> i had her doing 0.5mm TQFP for practice last time she was over and after the first two sides she seemed to be doing pretty decently
<azonenberg> the fringe benefit of the whole deal is that she usually brings her dog when she's over, and my wife really misses having one around the house lol
<azonenberg> We're planning to get one, but wanted to finish the rest of the construction first
<azonenberg> but if said dog is just an occasional visitor we don't have to worry about him getting hurt while we're tearing out an old door or something
<azonenberg> since we'd just do the work on other days
<azonenberg> Anyway, i probably need a few more training sessions but i'm gonna put her to work doing a run of two or three integralsticks later in the month
<azonenberg> as i have a couple projects coming up that will need them
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<ZirconiumX> The Quartus timing analyser is great fun when you've got to map its suggestions back to nmigen
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<whitequark> can nmigen be improved in this regard?
<ZirconiumX> Give me a bit and I'll copy the suggestions over
<ZirconiumX> whitequark: if I'm doing anything dumb in nmigen do say so
<ZirconiumX> The top ten timing closure recommendations are basically all to do with the fsm_state.00 to r_y_inc[10] path
<ZirconiumX> I mean to be fair, I got the kind of shitty FSM to hit 90MHz without touching the synthesis options
<whitequark> looks like your critical path is the comparison
<whitequark> y0b<y1b
<whitequark> overall it doesn't look super unreasonable to me?
<whitequark> you could pipeline the computation of y0b maybe
<ZirconiumX> This is kind of a straight conversion of example C++ code to an FSM, so
<ZirconiumX> Hah, turning some of the stuff in START into an extra state brings Fmax up to 144.89 MHz
<ZirconiumX> Which is pretty huge
<ZirconiumX> Thanks, whitequark
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<ZirconiumX> 157.63 MHz, after some tweaking. I'm happy with this, I think
<whitequark> that's not bad
<ZirconiumX> It's still complaining about timing slack, but oh well :P
<ZirconiumX> It probably wants me to add clock constraints
<ZirconiumX> Yeah, it needs more work to tighten timings
<ZirconiumX> whitequark: Given it's complaining about timing slack from fsm_state.000 to r_dx, I'm assuming that means State 0 i.e. START?
<ZirconiumX> (updated with current code)
<whitequark> what is "fsm_state.000" exactly
<whitequark> that signal is not in the code
<ZirconiumX> By the looks of it, it's referring to "fsm_state"
<ZirconiumX> I'll upload the current Verilog
<ZirconiumX> Done, same URL
<whitequark> why don't you upload the timing report?
<ZirconiumX> Also done; timing.txt which is the full timing analyser report
<ZirconiumX> In all of its weirdness
<ZirconiumX> ...Why is it instantiating a 1GHz clock when I specified a 150 MHz clock?
<whitequark> specified how
<ZirconiumX> create_clock -name "clk" -period 6.666ns [get_ports {clk}]
<ZirconiumX> In the SDC
<whitequark> that's generated by nmigen, right
<ZirconiumX> Oh
<ZirconiumX> Critical Warning (332012): Synopsys Design Constraints File file not found: 'clk.sdc'. [snip]
<ZirconiumX> Do they really need to be this picky with filenames?
<ZirconiumX> Let's try again
<ZirconiumX> Right, 149.77MHz, with some very minor timing slack problems
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<ZirconiumX> Okay, timing report has been updated
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<GenTooMan> out of curiosity per the "greenpak" conversation I looked at those, kind of a strange mix of things. I'm not sure "what I could do with one", they do make one very tempted to "try all sorts of things" however. :D
<whitequark> it's glue logic
<whitequark> apple uses a lot of greenpak chips on their boards
<ZirconiumX> I was wondering "why not use a CPLD", and then I found out the sheer size of a GreenPAK
<ZirconiumX> Or lack thereof
<whitequark> they're very cheap and OTP capable
<ZirconiumX> Though it does frustrate me a little that synth_greenpak4 errors out if you try to synthesise something too big instead of letting you see how big the end result is
<whitequark> does it?
<ZirconiumX> ERROR: Insufficient number of LUTs to map all logic cells!
<whitequark> oh, right, that's abc
<whitequark> the reason it does that is um
<whitequark> because it will use smaller LUTs if it runs out of larger LUT
<whitequark> so you can't actually get a sensible "size of design"
<ZirconiumX> Darn
<ZirconiumX> It's interesting to compare the gate list of quartus_map vs Yosys's synth_intel
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<ZirconiumX> When the latter works, anyway :P
<ZirconiumX> With such highlights as quartus_map producing a LUT7
<ZirconiumX> 7 LUT7s, actually
<ZirconiumX> 361 LUTs for Quartus, 515 for Yosys; 153 DFFs for Quartus, 165 for Yosys
<whitequark> comparing LUT counts isn't very representative
<whitequark> because yosys with -abc9 optimizes for delay, not area
<ZirconiumX> synth_intel has no -abc9
<whitequark> oh
<whitequark> yosys without -abc9 just has horrible QoS
<ZirconiumX> Because IIUC ABC9 requires timing models of the FPGA cells
<ZirconiumX> Which we don't have
<daveshah> Well, you can use it without but that would be missing the point of it somewhat
<ZirconiumX> It is pretty neat that Quartus can explain why some things got removed in synthesis
<ZirconiumX> It comforts me greatly that not even Quartus can agree on what they call their primitive cells
<ZirconiumX> wq: is there a way to suppress the nMigen attribute spam for Verilog? Quartus spams the log with warnings about unrecognised attributes
<whitequark> well, it's not spam, it's telling you where everything comes from
<whitequark> anyway, no, there's currently no option to suppress that
<azonenberg> sure there is
<azonenberg> it's called "grep" :p
<whitequark> that'd suppress all attributes, not just the ones nmigen produces
<azonenberg> just means more precision grepping :p
<azonenberg> Only half kidding
<daveshah> You can do `write_verilog -noattr` as a nicer grep
<daveshah> Or `-attr2comment`, iirc
<ZirconiumX> Hurray, my line algorithm thing meets timing!
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<GenTooMan> whitequark I can see apple using greenpak's a lot. They
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<mwk> ZirconiumX: attrmap pass can remove attributes matching a pattern
<ZirconiumX> Mmm
<ZirconiumX> By the way mwk, did you look at my code? It's changed a bit since I last linked it, but it's now at up to 170MHz
<mwk> not yet, been busy with... things
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* mwk takes this opportunity to learn nmigen
<adamgreig> how much more faff is an ecp5 to design in than ice40? i've done a handful of ice40 boards now but would like to play with ecp5
<adamgreig> it seems like bigger packages, another voltage rail, more strapping pins for more complicated configuration
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<azonenberg> adamgreig: honestly the hard part with FPGA boards isn't the minimum connections
<azonenberg> it's figuring out all of the rules regarding which pins can be used for what
<azonenberg> differential pairs, clock inputs, etc
<adamgreig> ice40 was pretty easygoing on that sort of thing
<adamgreig> some differential inputs, two pll cells
<azonenberg> yeah, when you get to a big xilinx part it's... a bit more complicated
<adamgreig> admittedly the pll stuff is a nuisance as it's very poorly documented which inputs to use to go directly to pll and that you can't use the io and the pll at the same time etc
<azonenberg> ecp5, although i havent used it yet, is likely somewhere in the middle
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