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<TD-Linux> adamgreig, btw I didn't realize you were the one doing a lot of the stm32 rust work. thanks :D
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<tnt> daveshah: is there some primitive or option or something to set the next boot address ?
<daveshah> tnt: ecpmulti should do that
<tnt> I see ecpmulti can build an aggregate of images, but really I just want to manually set the boot address so I can build individual bitstreams for the various images independently of each other (and then manually flash them at the right spot)
<daveshah> Then you'll have to patch the .config file
<daveshah> Add something like `word: BOOTADDR xxxxxxxx` into EFB1_PICB1 with xs being the MSB of the 24-bit address
<tnt> .tile CIB_R70C7:CIB_EFB1
<tnt> ?
<daveshah> No, EFB1_PICB1
<daveshah> You might need to add it
<daveshah> It should be .tile MIB_RyCx:EFB1_PICB1
<daveshah> with Y and X coming from the tile grid for the device
<tnt> Ok, I think I might just write a ecpsetboot utility that actually used the database rather than hack something up :)
<tnt> and copy the config code from ecpmulti
<daveshah> Actually, I think this is the only option
<daveshah> As you need to add a multiboot flag to the header too
<daveshah> I didn't write ecpmulti so I'm not the best person to know, but copy what it does setting multiboot to yes in the options too
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<tnt> If anyone wants to test an experimental ecpbram that's been exhaustively tested on a grand total of 1 bitstream so far ... https://github.com/smunaut/prjtrellis/commit/a3fa02be616030f64e48f8fcfae8060d7c095010
<ZirconiumX> tnt: better than the Mistral tools so far :P
<tnt> ZirconiumX: is that the projects for Altera ?
<ZirconiumX> Yep
<ZirconiumX> Cyclone V specifically
<tnt> Is there a project page ? google's failing me on this one.
<ZirconiumX> the """page""" is https://github.com/ ZirconiumX/mistral
<ZirconiumX> Minus whitespace
<ZirconiumX> tnt: it's in very early stages of development as I a) get the hang of reverse engineering things and b) haven't gotten very far
<tnt> ZirconiumX: yup got it :)
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<ZirconiumX> whitequark: so with you adding machxo2 support to nmigen, I have to ask: how awful are its primitive names?
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<whitequark> ZirconiumX: same as on ecp5
<whitequark> some suffixes changed
<ZirconiumX> Oh god
<daveshah> The suffix thing is similar to Xilinx
<daveshah> Increased letter at the end is equivalent to "number after E" in Xilinx
<daveshah> Sometimes you get some cute ones by adding letters like JTAGG
<whitequark> ecp5 is generally similar to xilinx, and they're both pretty reasonable overall
<whitequark> altera though did something batshit insane instead at every opportunity
<ZirconiumX> Eventually the PTSD will set in and I'll just be numb to it all
<ZirconiumX> "Oh, you picked yet another inconsistent primitive name. Okay."
<ZirconiumX> This brings me to a question for daveshah: is Yosys' module naming case-sensitive?
<whitequark> counterpoint: i have actual ptsd and thats not how it works
<ZirconiumX> Okay, I apologise for the hyperbole
<whitequark> we should have a separate word for that imo. but anyway
<daveshah> ZirconiumX: never tried, but I guess it is as Verilog generally is
<ZirconiumX> Oh goody. Quartus primitive names are not case sensitive.
<whitequark> there's a pass that matches case on parameters iirc
<whitequark> not sure if it works on instances too
<daveshah> It would be easy enough to do something like that
<ZirconiumX> I also feel like I would have to reimplement half the Quartus IP cells
<daveshah> Yes, this is unavoidable with the Quartus IP block approach
<whitequark> i feel like a lot of it looks scarier than it is
<whitequark> e.g. remember the altddio blocks?
<whitequark> that i feared would not be easily reproducible?
<whitequark> looks like it's just a single FF and then a single (*altera_attribute*)
<whitequark> and you can get the exact same result as their megafunction
<ZirconiumX> I looked at the simulation library and couldn't find anything for it which didn't look horrifying
<ZirconiumX> But yeah, you're probably right
<whitequark> can you link me the simlib?
<whitequark> that specific megafunction ideally
<ZirconiumX> https://github.com/asicguy/gplgpu/blob/master/hdl/sim_lib/altera_mf.v which is too big to display on GitHub
<whitequark> oh right i have quartus
<ZirconiumX> Quartuses in fact
<whitequark> i'm not sure wtf this code is doing but it seems related
<whitequark> quartus whines about ignoring DDIO_INPUT_REGISTER on Cyclone-III
<ZirconiumX> Hmm, that's a useful tidbit
<whitequark> look at /opt/quartus/13.1/quartus/libraries/megafunctions/altddio_in.tdf
<whitequark> is that... some sort of NIH verilog variant they have
<ZirconiumX> My mind stubbornly refuses to parse AHDL, sadly
<whitequark> i guess it's harder to be worse than verilog so it's probably actually better
<whitequark> gotcha
<whitequark> ZirconiumX: what it does for cyclone is it simply instantiates a few DFFEs
<whitequark> in exactly the way you think it would
<ZirconiumX> "In contrast to HDLs such as Verilog and VHDL, AHDL is a design-entry language only; all of its language constructs are synthesizable." <-- a vendor actually got something right for once
<whitequark> one clocked by inclock, one by !inclock
<whitequark> and then it does this:
<ZirconiumX> Yeah, that makes sense
<whitequark> which tells the fitter to stuff input_cell_L next to the IO pin
<whitequark> which is pretty much what the docs say, anyway
<ZirconiumX> That's useful to know, thank you
<whitequark> oh and it looks like on cyclonev the AHDL is the exact same
<whitequark> and fitter just packs the DDIO registers into the IOB
<whitequark> so tbh it would be entirely possible to skip all the megafunction junk in nmigen, there is only one opt-out for stratix afaict
<whitequark> i'm kinda confused as to what happens for arria and stuff
<ZirconiumX> I've generally found that Arria is more like Cyclone than Stratix
<whitequark> ok, so maybe they map it to cyclone somewhere inside?
<ZirconiumX> Stratix seems to do its own thing in the name of performance
<ZirconiumX> Possibly, yeah
<ZirconiumX> (for example the ALM design seems to originate in the Stratix II, which made it to Cyclone III/V.)
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